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Research On Acceleration Of Target Detection Algorithm For Cabled Underwater Robot

Posted on:2023-01-15Degree:MasterType:Thesis
Country:ChinaCandidate:B P ZhangFull Text:PDF
GTID:2558307145465304Subject:Traffic Information Engineering & Control
Abstract/Summary:PDF Full Text Request
With the frequent exploitation of marine resources by human beings,underwater robot has attracted much attention because it can replace human beings in underwater operation.Underwater target detection is an important tool for underwater robot to obtain underwater operation information by perceiving the external complex underwater environment.According to the special requirements of low power consumption and underwater robot target detection,this thesis designs a target detection algorithm acceleration board based on ZYNQ series FPGA as embedded processing,improves the target detection algorithm according to the internal resource characteristics of FPGA,speeds up the model inference,designs convolutional neural network operation accelerator in Verilog language.First of all,this thesis designs and develops the Gigabit Ethernet transmission circuit and DDR3 memory interface circuit of the accelerator board,meets the requirements of small size and multi-layer lamination,ensures the signal integrity and high-speed signal routing theory,and designs and produces PCB for Gbit/s level transmission of accelerator board.Secondly,after analyzing the structural characteristics of the YOLOv4 target detection algorithm and the Shuffle Net V2 lightweight feature extraction network,this thesis improves their lightweight,and realizes the data quantization in the internal calculation process of FPGA;at the same time,this thesis chooses to use RTL-level accelerator design based on Verilog language,builds the CNN operation accelerator to accelerate the inference process of the network model.According to the internal resources of FPGA chip and the characteristics of pipeline parallel operation,this thesis analyzes and optimizes the parallel dimension of the accelerator.Finally,this thesis carries out relevant experiments to test and analyze the data transmission function,the target detection algorithm and the acceleration performance of the board.According to the experimental results:(1)The target detection acceleration board can still achieve gigabit-level data transmission,under the condition of ensuring the size and volume as small as possible;(2)The detection speed of the improved YOLOv4 target detection algorithm is greatly improved,and the average accuracy decreases slightly;(3)The improved YOLOv4 algorithm accelerated by the accelerated board hardware has an average power consumption of 2.1W,which is 7.17 times higher than the power consumption ratio of the GPU platform,and has a higher performance advantage compared to the GPU platform.Compared with other related works,the research work related to target detection acceleration design proposed in this thesis still has obvious performance advantages and mobile deployment advantages.
Keywords/Search Tags:FPGA, YOLOv4, Parallel Operation, Hardware Acceleration
PDF Full Text Request
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