Realization Of 5G-NR Downlink Synchronization Based On Vector Processor

The 5th Generation Mobile Communication(5G),as the latest generation of mobile communication technology,has the advantages of high transmission rate,high reliability and low delay.With the continuous evolution of 5G standards,research on 5G has become a hot trend in the field of information and communication.Cell search and downlink synchronization are the first steps after the 5G terminal is powered on,and are also the key links that determine the performance of the wireless communication system.The Physical Broadcast Channel(PBCH)mainly carries the Master Information Block(MIB),and its accurate reception is the guarantee for the terminal to successfully access the network.Therefore,it is of great significance to study 5G cell search and downlink synchronization and PBCH reception.This thesis starts from the practical application background of 5G New Radio(NR)physical layer chip research and development,and focuses on the problems of 5G-NR cell search,downlink synchronization and PBCH reception.In addition,based on the digital signal processing(Digital Signal Processing,DSP)platform,the fixed-point implementation of the vector parallel acceleration scheme is completed.First of all,this thesis studies the influence of time offset and frequency offset on OFDM system in Orthogonal Frequency Division Multiplexing(OFDM)system,and introduces the wireless frame structure configuration and time-frequency domain resources of 5G-NR based on the communication protocol standard,and then studies the generation of Primary Synchronization Signal(PSS),Secondary Synchronization Signal(SSS),Demodulation Reference Signals(DMRS),resource mapping in time-frequency domain,and PBCH load generation and SS/PBCH structure and its resource mapping in time-frequency domain.Secondly,this thesis builds a simulation link platform for 5G-NR cell search,downlink synchronization and PBCH reception,and simulates and studies various algorithms,including coarse timing synchronization algorithm,frequency offset estimation algorithm,fine timing synchronization algorithm,and SSS detection algorithm,DMRS blind detection algorithm,channel estimation algorithm,channel equalization algorithm and Quadrature Phase Shift Keying(QPSK)soft demodulation algorithm,and then analyzes the performance of various algorithms.Moreover,under the conditions of Additive White Gaussian Noise(AWGN)and Tapped Delay Line(TDL)channels,this thesis compares and analyzes the performance and computational complexity of two different coarse timing synchronization algorithms,three different frequency offset estimation algorithms,and two different channel estimation algorithms,which pro-vide a reference for the DSP implementation of the subsequent vector parallel acceleration scheme.Finally,based on the algorithm and process of the simulated link platform,based on the DSP CEVAXC4500 processor platform,this thesis designs a vector parallel acceleration scheme for 5G-NR cell search and downlink synchronization and PBCH reception.For each module in the process,the fixed-point processing of each module is realized by using the parallelism of Vec-C instruction,and the code coding and function verification are completed in the CEVA-Tool Box software development environment,and the complexity is optimized at the same time.The results show that the detection results of the vector parallel acceleration scheme designed in this thesis are consistent with the expected results,and the processing efficiency is improved,which verifies the feasibility and rationality of the scheme and meets the application requirements.