Research On 5G Polar Coding Technology And FPGA Implementation

Polar codes,the first coding scheme that has been strictly proven to achieve the symmetric capacity of binary input memoryless discrete symmetric channels,are gradually recognized by academia and industry due to their simple encoding and excellent performances.In the5 G enhanced mobile broadband(e MBB)scenario,polar codes are selected as the coding scheme for the control channel,physical broadcast channel,and Side Link by 3GPP.Based on the background of 5G mobile communication,this thesis studies the algorithms design and hardware implementations of polar codes.The main work is as follows.Firstly,we summarize the domestic and foreign research results of polar codes,mainly about decoding algorithms and hardware implementations.The performance of polar codes is mostly determined by the code construction methods,decoding algorithms,and concatenation schemes.Therefore,this thesis introduces the principles of these algorithms and presents the performance simulation results.In addition,we reveal the design of concatenated polar codes in various scenarios of 5G NR in detail,including parameters selection of concatenated encoding,position calculation of PC bits,DCRC interleaving pattern design,and rate matching method.Secondly,we finish the implementation of CA-Polar,PC-CA-Polar,and DCRC-Polar encoders in 5G with field programmable gate array(FPGA).We propose a semi-parallel architecture for the implementation of polar encoder,which greatly reduces the resource occupation and avoids generating critical paths.In order to improve the hardware efficiency,the encoder resists repeatedly calculating the information bit position and the DCRC interleaving pattern with the same encoding parameters.FPGA implementation results show that the(512,256)CA-Polar encoder can work with 316 MHz stably,and the throughput is about156 Mbps.Finally,we accomplish the FPGA design of CA-SCL,PC-CA-SCL,and DCA-SCL decoders in 5G.In order to study the optimal fixed-point quantization method of decoders,this thesis compares the frame error rate(FER)performances of the three concatenated polar codes with various quantization schemes.The simulation results show that the decoder can achieve excellent FER performances with the least waste of bit width if the channel received log likehood ratio(LLR)adopts 4-bit quantization and the internal LLR adopts6-bit quantization.Aiming at improving the resource utilization efficiency,we propose a semi-parallel SCL decoder structure with a parallelism of 32,which reduces the number of processing element by about 94% compared with the fully parallel structure.According to the characteristics of SCL decoding,we ”prune” the sorting algorithm used in path metric sorting,which reduces 40% of the critical path length.Furthermore,the decoder adopts a parallel CRC check method and inserts multi-level buffer register to reduce the time delay.As a result,the decoder only needs 2656 clock cycles to accomplish the(1024,512)CAPolar decoding.The throughput can approach 16.8 Mbps when the decoder work with 43.5MHz.