| Array radar is a complex equipment consist of multiple subsystems with the core of signal processing.This paper is based on one system of array radar,which takes domestic Fudan micro field programmable gate array(FPGA)as the main control chip and chooses timing control and signal preprocessing board as the hardware platform.This paper expounds the implementation process of timing control and preprocessing in array radar system detailly.Firstly,starting with the basic process of array radar signal processing,this thesis studies the principle of digital down conversion and digital beam forming in signal preprocessing combined with the array model.According to the system requirements,this thesis constructs a hardware processing platform for cooperative working with multi-boards.The timing control board takes Fudan micro FPGA 7K325 T chip as the core,which designs and realizes the generation and switching control of radar timing signal;Taking the analog-to-digital conversion chip AD9739 as the core,the intermediate frequency signal is generated by digital method;Through the rich input output port resources of FPGA and the integrated intellectual property core,the design of Low-speed serial port and high-speed Ethernet communication interface is realized.With Fudan micro FPGA 7V690 T chip as the core,signal preprocessing is divided into analog-to-digital acquisition board and digital beam forming board.Data communication adopts serial high-speed bus for transmission,and the maximum throughput can reach 80 Gbps.The MF echo signal is sampled by AD acquisition board,and the sampled data is processed by digital down conversion and polyphase filtering to obtain the baseband signal.The baseband data is packaged and transmitted to the DBF board through 9-channel optical fiber communication interface.After data analysis,the DBF board performs digital multi-beam forming and packages for in-phase and quadrature baseband signals in pitch and azimuth dimensions,and the data is sent to the signal processing unit through 4-channel serial rapid input/output.In addition,according to the array requirements,this thesis proposes a correction scheme combining analog and digital for large-scale array radar,and analyzes the correction results in detail.Meanwhile,this thesis designs synchronization and self calibration for the sampling error code of high-speed ADC chip,designs and tests the verification for the possible communication error code in the system,responds quickly to the system fault problem and reports it to the terminal for display.The algorithm is optimized,and the results of FPGA hardware processing are compared by MATLAB,and the relative error is reduced to the order of magnitude.In this thesis,domestic FPGA is used as the hardware development platform to design the timing control and preprocessing system in array radar.Experiments show that the system has the advantages of high bandwidth,stable transmission and fast algorithm processing speed.It has reference value for the engineering development of timing control and frontend preprocessing system of large-scale array radar. |
