| The continuous increase in the complexity of IC design makes the corresponding cost and simulation verification period continue to increase.In order to speed up the debugging speed,emulation technology emerges as the times require.Combining the advantages of two basic simulation verification technologies,software simulation and hardware acceleration,it can effectively reduce design costs and verification cycles.This thesis will optimize the memory compilation of the hardware acceleration platform based on the emulation technology combined with engineering practice.In the emulation,the hardware platform adopts FPGA as the acceleration platform.When a memory resource is used,the FPGA’s synthesis tool will synthesize it into the FPGA’s internal BRAM.The expansion of the dut’s area makes the BRAM resources unable to meet the IC design requirements.Expanding the memory resources available to the FPGA has become the focus of the current design.This thesis proposes a memory compilation method,which can map the ram resources used by users to the off-fpga memory,thereby expanding the memory resources of the FPGA.This subject originates from an enterprise project,and mainly designs and researches the netlist-level memory compile method applied to the emulator.The main contents are:(1)In order to map the memory resources in the DUT to the off-fpga memory,an overall implementation scheme of the external DDR of the DUT memory is proposed.The design idea is to connect the access signal to the ram in the DUT to the DDR controller through the BRAM2 AXI bridge to connect to the external DDR.In this way,the DUT’s access to ram can be mapped to the external DDR port on the hardware platform.At the same time,in terms of user behavior,the DUT still accesses ram,maintaining functional consistency,thereby effectively realizing memory expansion;(2)Appending the overall scheme described in(1),this thesis implements a specific scheme for memory compilation based on the architecture and hardware resource parameters of xilinx’s FPGA.In terms of logic,develop the hardware system and various required function modules with BRAM2 AXI bridge as the core.The generated BRAM2 AXI bridge schedules multiple groups of 64-bit bit-width access timings,adapts to the interface bit width of the DDR controller,and improves the efficiency of ram read and write timings being converted into AXI access timings.The actual measurement results show that the overall DDR bandwidth utilization is increased by about 30% by converting 70% of the ram reading and writing below 64-bit width in the DUT into 64-bit wide DDR access;(3)The memory compilation software part is another important content to be dealt with in this thesis.This thesis designs the memory compiler corresponding to the automatic netlist processing system.The memory compiler analyzes and processes the EDF netlist file,studies the structure of the user’s ram and the splicing and merging algorithm,merges multiple ram accesses with different bit widths and depths into multiple sets of 64-bit wide BRAMs,and pulls the BRAM ports to the network.top level of the table.On this basis,the BRAM port,BRAM2 AXI bridge,DDR controller,etc.are connected with signals to realize the connection between ram and external DDR.The actual measurement results show that the FPGA memory resources are expanded from the upper limit of 16 MB to more than 2GB.(4)On the basis of completing the distribution work,integrate all the designs into the emulation to realize the function of the memory compilation.The memory compiler takes several minutes to run,which is significantly more efficient than the hours it takes to manually process the memory compile process.Use the memory compiler to process the original netlist,connect the access signal of the corresponding ram to the top layer,insert the BRAM2 AXI bridge,DDR controller,etc.,and then compile and simulate the board through a complete project.The actual measurement shows that the user’s access to ram is converted into DDR read and write,and the DDR read and write data collected by the backdoor is consistent with the function envisaged by the original netlist,which is in line with the design expectations.The function of mapping DUT internal ram to external DDR in the memory compilation designed in this paper can provide a technical reference for the research on memory expansion of FPGA-based emulation. |
