Design Of PCIE-Based Multi-Neural Network Processor Board Data Exchange System

Artificial intelligence(AI)has developed rapidly in recent years,and there are two main implementation methods,namely,based on cloud server(Graphics Processing Unit,GPU)and based on terminal equipment embedded AI processor(Neural-Network Processing Unit,NPU)implementation.The NPU processor for terminal applications is a high-power,lowpower processor for AI applications that has appeared in recent years.Although NPU has been around for a short time,it has developed rapidly,which greatly meets the technical needs of terminal devices to realize AI applications,and is a hotspot of current research and application.The use conditions of terminal equipment require that when achieving high-performance computing power,the constraints of processor computing power,power consumption,storage space and volume need to be met.At present,the computing power of highperformance NPU is between 5TOPS-30TOFS,which mainly implements AI applications with a single function.However,for industrial,security and military applications,there is an urgent need for composite AI applications that require high computing power.It is required to realize different types of AI model calculations under the condition of ensuring real-time performance,which is also a new direction for the further development of NPU.Based on the single-core HHQJ-103 board developed by the independent entrepreneurial team of Xidian University,the paper constructs a 4-core HHQJ-104 board interconnected by switching fabric,which realizes the parallel processing and exchange of multiple artificial intelligence tasks.The main work of the thesis includes:(1)Design a switch circuit structure for scalable hybrid PCIE and RapidIO;(2)Design a data frame structure suitable for this structure,to achieve PCIE fast interrupt response,and standard Compared with PCIE,the interruption time is reduced by more than 90%;(3)The multi-AI task processing board for industrial inspection and security field is realized by using FPGA chip,and tested and verified.It solves the problem of task scheduling and data exchange conflicts encountered when multiple boards are integrated and used,and improves the reliability and operation efficiency when multiple boards are stacked and expanded.The test results show that after adopting the system designed in this paper in the semiconductor test equipment product line of XX Company,the overall test efficiency is increased by 13%compared with the original system,and the power consumption of the whole machine is reduced by 8%compared with the original solution.In the large-scale semiconductor measurement process,the test efficiency of the production line is significantly improved,and the energy consumption in the batch test process is reduced.The main innovations of the paper are:(1)According to the process needs of data exchange through PCIE in the multi-neural network processor system,a simple and feasible data packet format is customized.It ensures the reliability of data transmission and the simplicity of operation,and realizes fast interrupt response;(2)The combination of wormhole switching technology and circuit switching technology is adopted in the design,and the use of wormhole switching technology requires less storage space At the same time,by virtue of the characteristics of high bandwidth utilization of circuit switching technology,an efficient data exchange process is realized.