Research And Design Of A Cryptographic Coprocessor Based On RISC-V

With the gradual rise of AIo T applications,cryptography,as a powerful tool for securing Io T communications,has received more and more attention from researchers and the industry at home and abroad,and accordingly new requirements are put forward for cryptographic algorithm implementation schemes.However,the software implementation meets high flexibility and low hardware cost requirements,but the speed of the algorithm is slow,while the application-specific Integrated circuit implementation greatly improves the algorithm performance,but also pays the price of high hardware cost and low flexibility.Cryptographic implementations have failed to balance flexibility,performance,and cost.To this end,this thesis proposes a cryptographic coprocessor implementation based on the RISC-V architecture.For the hybrid encryption scenario in the field of information security,the overall acceleration of block cipher,stream cipher,public-key cipher and hash algorithm improves cryptographic computing efficiency and improves cryptographic acceleration range at a compromised hardware cost.The main research contents are as follows:1)Aiming at the problem of difficult expansion of the existing research cryptographic operation unit,based on an open-source RISC-V processor,the simple and efficient expansion method of the cryptographic coprocessor is studied.2)Aiming at the lack of generality of existing cryptographic operation units,the implementation process and operation characteristics of various cryptographic algorithms are analyzed,and five time-consuming operations that need to be accelerated are extracted.Hardened modular multiplication,Sub Byte,permutation,hash compound operation and serial XOR,and designed 10 cryptographic instructions according to the operating characteristics.3)The thesis focuses on optimizing the implementation scheme of modular multiplication and improves the high-base Montgomery modular multiplication algorithm by adopting the idea of partial carry-save adder.A high-performance modular multiplier circuit design based on SCSF multiplier-accumulator is proposed,focusing on improving the computational efficiency of public-key cipher.The cryptographic coprocessor is verified under the Nexys Video FPGA development board of the Xilinx Artix-7 series.The evaluation results show that,compared with the software implementation,the cryptographic coprocessor designed in this paper has a speedup ratio of2.94 to 26.8 times for AES,DES,SM4,SHA-1 and A5-1 algorithms;and compared with the ASIC implementation,only 10.36% of the hardware overhead can achieve 26.83% of its RSA encryption performance,which fully shows that this design has certain comprehensive advantages in algorithm flexibility,cost and performance.