| Accelerator devices have important application value in the fields of scientific research and industrial production.With the continuous development of science and technology and the in-depth exploration of the microscopic world,accelerators are developing in the direction of larger scale and higher energy,and the requirements for synchronous control of various components are getting higher and higher.Therefore,a larger fan-out is proposed for the clock system.capability and higher synchronization accuracy requirements.However,the clocks used by accelerators are often of special frequency,which cannot be obtained by frequency division of common clocks.Therefore,the high-precision distribution and synchronization of accelerator clocks has always been a challenging research topic.Early accelerator clock systems were mostly clock distribution networks customized for specific devices and clock frequencies,which had problems such as difficult expansion,high cost,and poor compatibility.In order to meet the needs of modern applications,domestic and foreign institutions are actively developing the distribution and synchronization of accelerator clocks based on White Rabbit technology.WR has attracted wide attention due to its scalability,high-precision clock distribution and synchronization.However,the standard WR protocol can only realize the distribution and synchronization of the reference clock(62.5 MHz/125 MHz),and cannot be directly applied to the special frequency point of the accelerator.Therefore,this paper further introduces Direct Digital Synthesis(Direct Digital Synthesis,DDS)technology to solve the problem of special frequency points.However,limited by the WR hardware link delay and the complex analog circuit of DDS,this technology currently only achieves a special frequency clock synchronization accuracy(skew jitter)of 20 ps and a phase difference change between nodes of about 100 ps(skew).The nextgeneration accelerator experiment puts higher demands on the clock system,so it is necessary to research and develop higher-precision accelerator clock distribution and synchronization technologies.In this thesis,aiming at the demand of modern accelerator devices for the clock system,on the basis of analyzing the limiting factors of clock synchronization accuracy,it is realized based on the high-speed transceiver and improved DDS technology in the high-performance FPGA.The circuit design of self-adaptive high-precision distribution and synchronization of any special frequency clock is realized.On the basis of using the precision delay adjustment unit in the FPGA high-speed transceiver and the delay fixing technology of the transceiver circuit to realize the high-precision distribution and synchronization of the reference clock,a TDC technology based on FPGA is proposed.The new extraction method of all-digital special frequency clock feature information converts real-time frequency and phase extraction into high-precision time measurement,and adopts the sliding average method to ensure high-precision extraction of feature information and high-frequency update of feature information.In addition,it avoids the use of DDS-based complex analog circuits on the master node,reducing circuit complexity,and then cooperates with slave node waveform recovery to finally complete the self-adaptive high-precision distribution and synchronization of arbitrary frequency clocks.On the basis of method research,this thesis completes the hardware electronics design and performance evaluation test of the high-precision clock system.The test results show that this design realizes the special frequency adaptive synchronization function and reaches the expected design index.Under laboratory conditions,the special frequency clock distribution and synchronization achieves a synchronization accuracy better than 15 ps.About 20 ps,within the temperature range of 50 ℃,the phase difference between nodes changes less than 20 ps,and the transmission of time stamp and instruction data is completed... |
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