The Design Of AFDX Network Clock Synchronization

AFDX(Avionics Full Duplex Switched Ethernet),as a new generation aviation communication bus,has the advantages of high transmission rate,good reliability and high certainty.It is currently used in the design of A380,Boeing787 and C919.Data integrity check is an important step to ensure the security of data transmitted on the AFDX network.If it cannot be guaranteed,it will affect the flight safety of the aircraft to a certain extent.Misoperations affect the flight safety of the aircraft and even cause catastrophic effects.The integrity of AFDX transmission data includes source integrity,bit integrity,sequence integrity,and time integrity.Among them,the research on the source integrity,bit integrity,and sequence integrity of data is relatively mature,and clock synchronization design is an important part to ensure time integrity.The related research is still in its infancy,and there are no relevant mature products in China Can be used in civil aircraft.Therefore,it is of great significance to study the integrity of the avionics transmission data,especially the time integrity.This subject is based on the research of domestic and foreign AFDX clock synchronization and Ethernet clock synchronization related materials,combined with laboratory resources,design and complete a set of AFDX network clock synchronization scheme based on IEEE-1588 protocol.On the basis of minimizing the network load caused by clock synchronization-related data frames,the clock offset between different AFDX end systems is acquired in parallel to improve the reliability of the time integrity check of AFDX network transmission data.In addition,considering that the software and hardware or the end system in the avionics system may be restarted due to human factors or physical reasons,resulting in the loss of local time and the inability to perform clock synchronization,this topic adds an end to the clock synchronization design.System local time recovery unit to ensure that the AFDX system can perform clock synchronization and complete the time integrity check of the transmitted data under any circumstances.In this paper,the basic research of AFDX bus protocol and Ethernet clock synchronization protocol is firstly carried out.Then,based on the time integrity check of AFDX network transmission data and the synchronization principle of IEEE-1588 protocol,an end system based on the relative time deviation list is designed and proposed.Obtain the clock clock deviation plan;After that,complete the detailed design based on the proposed design and design the circuit through RTL code;Finally,verify the designed circuit from the bottom up to verify that it can achieve the expected function.