Research On The Circuit Design And Anti-Single Event Transient Hardening Of LDO

Low-dropout linear regulators(LDO)are widely used in large-scale integrated circuit power management systems due to their relatively simple structure,low noise and low power consumption,and strong stability.SerDes,the high-speed serial transmission interface,is the most commonly used information and communication technology today,and the power management system also uses LDO circuits.Different from LDOs in conventional application scenarios,LDOs in high-speed digital-analog hybrid circuits no longer blindly pursue high gain and high load capacity,but focus more on the comprehensive requirements of circuit bandwidth,noise,and transient response.There are a variety of high-speed and non-high-speed modules in the SerDes circuit.Different functional modules have different requirements for the power supply.Therefore,in the design process,LDOs with different performances should be designed separately instead of using the same high load capacity.Not only that,the aerospace-grade SerDes circuit not only has strict requirements on speed,but also needs to consider the complex radiation conditions in the working environment for radiation-resistant hardening design.After the LDO circuit reaches the basic performance index,the radiation effect of the circuit should be fully analyzed and the anti-radiation hardened design of the analog circuit should be carried out,so as to achieve the goal of stable and efficient work.This article designs three LDOs for different modules for the high-speed SerDes circuit to meet the different needs of each module in the high-speed circuit.Among them,the LDO of the in-phase quadrature device adopts a rail-to-rail input design to realize the function of adjustable output voltage.The LDO of the decision feedback equalizer introduces a charge pump structure,which improves the output swing of the error amplifier while reducing the noise from the power supply.The design of the asymmetric op amp reduces the area overhead by sacrificing part of the gain while reducing the impact of circuit mismatch.In the LDO of the non-high-speed module,the internal noise of the circuit is analyzed intensively,and the method of reducing the noise of the transistor by reducing the loop gain is demonstrated.The three types of LDO circuits use different frequency compensation methods due to their different structures.The LDO of the nonhigh-speed module uses a cross-cascode compensation capacitor,which effectively avoids the drawbacks of the traditional Miller compensation method.Through the simulation of various performance indicators,the LDO used in the in-phase quadraturer has a higher bandwidth to meet the needs of speed,and the LDO of the decision feedback equalizer has a better load adjustment rate to meet the needs of stability.Non-high-speed modules The LDO has large gain and strong load capacity.In addition,the three LDOs all have good performance in noise performance,and all have a phase margin of over86 deg.On the basis of fully studying the mechanism of the radiation effect of analog circuits,a general method for hardening the sensitive transistors of analog circuits single event transient(ASET)is proposed.In the analog circuit of bulk silicon process,if the transistor is exposed to high-energy heavy ion radiation,the electron-hole pairs ionized in the semiconductor material will cause the node voltage and well potential to fluctuate due to drift and diffusion.In response to this phenomenon,by setting a floating contact in the well(substrate)close to the sensitive transistor,the occurrence of the sensitive transistor SET can be effectively detected.Using the detection signal to drive the hardening circuit to work can accelerate the dissipation of the accumulated charge to achieve the effect of compressing the SET pulse width.This method has very small area overhead and basically has no effect on the original circuit.This method combines circuit-level and layout-level hardening ideas,and does not change the original process of the circuit.The simulation proves that this method can effectively detect the circuit SET,and the hardening performance of 68.7% can be achieved in the current mirror circuit.Using double exponential current source to simulate SET charge injection technology combined with heavy ion experimental data to analyze the sensitive nodes of the LDO circuit,it is determined that the nodes that need to be hardened in the LDO circuit are the error amplifier differential input transistors.Introduced another hardening method for the well(body)to connect to the source,and proved that the hardening method is effective through the op-amp circuit.The three LDO circuits designed above are hardened by the floating well contact and the well connected source respectively,and the hardening performance is verified by 3D modeling combined with spice’s mixed simulation.The results prove that the two methods have obvious hardening performance on the LDO of the in-phase quadraturer and the LDO of the non-high-speed module.The floating-well contact hardening method not only compresses the SET pulse width by 33%in the LDO of the in-phase quadraturer,but also reduces it.31% of the SET pulse amplitude is reduced,and 52% of the SET pulse amplitude is reduced in the non-highspeed circuit LDO.The method of connecting the well to the source can reduce the SET pulse amplitude by 67% in the LDO of the in-phase quadrature device.