Research On Single-Event Transient Radiation Hardened Method In 65nm Bulk Silicon CMOS Process

The IC(integrated circuit)is the core of the aerospace vehicle and it's working environment is full of various radiation sources.When the radiation sources strike through the integrated circuit,various radiation effects will be induced,which will lead to the failure of the spacecraft.There are many kinds of IC failure modes caused by the radiation effects.For latches,flip-flops and other timing units,the high-energy particles in the radiation environment hit the sensitive nodes of the circuit and deposit a large amount of charge on the incident trajectory.Then,these charges are collected by the circuit,which may cause the unit storage state to flip to form a Single-Event Upset(SEU);For the combinational logic circuit,the charge deposited by the incident particles can be collected by the sensitive node to produce a transient pulse.Then,these transient pulses propagate downward along the data path and may be captured by the timing units,eventually leading to circuit state damage and forming a single-event transient(SET).With the development of integrated circuit technology,the improvement of integration and the increase of working frequency,the soft errors caused by SET are gradually dominant and become the main failure modes in the nano-process and high-frequency circuit.In this thesis,the main factors affecting the soft error rate of ICs,namely SET,is studied in the 65nm bulk silicon CMOS process.Finally,the corresponding feasible radiation hardened methods are proposed.The simulation results show that these proposed method can effectively reduce the pulse width of SET,and thus reduce the possibility of SET causing soft errors,which has certain guiding significance to radiation hardened integrated circuit design in theory.The main works of this thesis are as follows:(1)By making full use of the existing research results both at home and abroad,the theory of SET is theoretically understood.Based on this,the simulation experiments are carried out by using Synopsys TCAD 3D computer-aided analysis simulation method,which will deepen the understanding of the SET effect and lay the foundation for the feasible measures of SET radiation hardened.(2)In this thesis,based on the existing method of adjusting the size of the recovery transistor,a method for splitting a hitted transistor into two parallel-connected and smaller-sized transistors is proposed.Considering the application requirements of high-performance low-power integrated circuits and the complexity of the actual radiation environment,this kind of radiation hardened method is simulated separately under different incident energy,incident angle and different power supply voltage.The simulation results show that this method can effectively reduce the SET pulse width and realize the radiation hardened effect without affecting the normal operation of the circuit.(3)On the basis of the first radiation hardened method,this thesis presents another radiation hardened method which use two transistors in series.The simulation results show that this method can effectively reduce the amplitude of the SET pulse.So,it has a certain reference significance for the study of the single-event transient radiation hardened method.