Design And Implementation Of Self-interference Digital Cancellation System

With the capability to receive and transmit signals at the same time and in the same frequency band,cofrequency co-time transceiver technology can not only boosts the spectral efficiency of wireless communication systems,but also improves the performances of radar jammers in many aspects,including interception probability,emitter recognition accuracy and jamming efficiency.However,the most significant challenge facing the development of co-time transceiver technology is the self-interference(SI)at the signal-receiving terminal.To address this problem,presently,the research on SI cancellation(SIC)has been classified into three domains,being spatial cancellation,analog cancellation and digital cancellation,respectively.Digital self-interference cancellation(DSIC),by virtue of its flexible and versatile processing and excellent performance,has acquired a high level of interest in the field of selfinterference cancellation.Aiming at the SI of co-frequency co-time transceiver system,the paper designed an efficient FPGA implementation structure of the digital cancellation system,followed by testing its cancellation performance.The study is as follows.For the SI suppression in narrowband co-frequency co-time full duplex(CCFD)wireless communications,the paper firstly evaluated the performance of the recursive least squares(RLS),least mean square(LMS)and its variants in a comprehensive manner,with respect to complexity,convergence speed,SIC ratio,and engineering implementation.On the basis of performance evaluation,the delayed LMS(DLMS)with the optimal performance is used to update the weight vector of the SIC structure.Next,after thorough consideration for implementation timing and complexity,we designed an efficient FPGA implementation based on the DLMS digital self-interference cancellation system,and presented the design process of the cancellation system as well as FPGA resource utilization.Finally,a DLMS-based DSIC simulation system was built by a FPGA hardware platform,followed by testing its performance in a wireless communication scenario.The results showed that the DLMS-based DSIC system can effectively suppress selfinterference signals under common modulation methods such as QPSK and QAM,while ensuring a relatively low bit error rate of the communication system.For solving the high output rate of the high-speed ADC chip and the performance deterioration of the conventional SIC method in the wideband transceiver-simultaneous radar jammers,we applied the wideband DSIC technology based on perfect reconfiguration to the jammers.Firstly,a wideband DSIC model based on perfect reconstruction was offered.Simultaneously,we designed an efficient FPGA implementation structure that consisted of AD,DA,digital channelizer and perfect reconfiguration modules,with thorough design process and FPGA resource utilization.Besides,the design of a wideband DSIC system for radar jammer was achieved by combing the implementation structure of DLMS algorithm.At last,the FPGA hardware testing platform was constructed,together with testing process and parameters of the cancellation system.The test results indicated that the wideband DSIC system not only improves the transceiver isolation of jammers when the enemy radar signal is linear frequency modulation(LFM),but also greatly strengthens recognition accuracy of their radar signal parameters.The above-mentioned research of this paper provides,in some way,a solution to the problem of selfinterference in Co-time Co-frequency transceiver systems.In practical engineering,the FPGA implementation structure of the self-interference cancellation technique presented in this paper could be applied in systems such as mobile communications and jammers.