Design And FPGA Implementation Of Phase Compensation Algorithm For Same Frequency Interference Cancellation In WCDMA Satellite System

Wideband Code Division Multiple Access(WCDMA) satellite signals have become the focus of military due to their high speed,strong anti-interference ability,wide coverage and freedom from geographical constraints.In the military electronic war,no matter put the weak target signal into the strong signal with the same frequency for confidential transmission,or when suffer from the same frequency interference we can still complete communication with our friendly army,they all need to extract the weak target signal from the interference signal with same frequency.The interference cancellation technology is often used in the project to achieve the weak target signal extraction under the same frequency interference.The key to interference cancellation technology is the parameters' accurate estimation of the same frequency strong signal.In this thesis,the digital phase locked loop(PLL) is used to accurately estimate and compensate the carrier phase of the same frequency strong signal,and the strong signal is completely mixed to the baseband.It lays the foundation for the subsequent completion of the strong signal reconstruction cancellation for the baseband and the work of extracting the weak target signal.Firstly,this thesis compares and analyzes several schemes,which use the traditional Costa PLL to achieve phase compensation.An improved PLL with eight carrier arctangent phase detector is designed to overcome the disadvantages of traditional Costa PLL,which can not eliminate the influence of amplitude and the low accuracy of phase detection.The improved phase locked loop can be used to complete the high precision estimation and compensation of the carrier phase of the WCDMA satellite signal.Then,the phase compensation algorithm for the same frequency interference cancellation in WCDMA satellite system is studied.The phase compensation algorithm in the same frequency interference cancellation consists of two functional modules.In the first functional module,a PLL composed of an improved digital phase detector,a digital loop filter,and a numerically controlled oscillator are applied to accurately estimate and compensate the carrier phase,and the target intermediate frequency signal is completely mixed to the baseband.In the second functional module,an improved decimation filter based on the idea of sacrificing the clock for hardware resources is proposed,which can reduce the signal sampling rate and relieve pressure in the follow-up baseband digital signal processing(DSP).The simulation of the phase compensation algorithm for the same frequency interference cancellation in WCDMA satellite system is completed by using MATLAB software,and the results of simulation verify the effectiveness of the phase compensation algorithm.Finally,the phase compensation algorithm for the same frequency interference cancellation,and the peripheral interface circuit of the Ethernet port and the external memory interface(EMIF) circuit are completed on the hardware platform of Altera's EP4SGX230KF40C2 chip by using the field programmable gate array(FPGA).A hardware test platform is set up,and the FPGA board test of phase compensation algorithm and peripheral interface circuit is completed according to the test scheme.The results of hardware test show that the FPGA implementation of phase compensation algorithm and peripheral interface circuit meet the design requirement.The design has good scalability and flexibility,which can be applied to the practical project.