Research And Design Of LDO Based On 0.13 μm CMOS Process

With the increase of chip integration and the development of system-on-chip(SOC),power supply noise and interference between different modules have become very serious,and a clean supply voltage is required to power these modules.Low dropout regulator(LDO)is the primary choice for powering these modules because of their lower circuit noise and higher power supply rejection ratio.In view of the research and development requirements of dual synchronous low-dropout DC-DC control chips,in this paper,SMIC 0.13 μm CMOS process was used to design a capacitor-less LDO with high power supply rejection ratio,which provides voltage for converter logic control circuit in DC-DC control chip.In this paper,the circuit structure of the bandgap reference circuit is analyzed,and the current summation type bandgap reference is designed,and the temperature coefficient and power supply rejection ratio of the circuit are optimized.For the error amplifier,the second stage is a two-stage op amp with non-inverting gain.After adding the power tube,the system becomes a three-stage structure,which improves the circuit loop gain and reduces the stability of the entire system.Theoretical analysis is carried out and the advantages and disadvantages of various frequency compensation methods are compared.The frequency of the LDO loop is compensated by the advanced Q-reduction circuit.The compensated LDO can maintain the loop stability under heavy and light load conditions.For the design of highpower supply rejection ratio of LDO,the influence factors of power supply rejection ratio in LDO are analyzed by intuitive analysis.The gate terminal voltage follows to improve the power supply rejection ratio of the circuit;in the power tube design,the feedforward path is added to further suppress the noise introduced by the gate-source voltage fluctuation of the power tube to improve the power supply rejection ratio of the circuit.In order to ensure the overall safety and reliability of the LDO circuit,an over-temperature protection circuit and an over-current protection circuit are also designed,so that the circuit can be turned off when it works under non-ideal factors.In this paper,the layout design of the LDO circuit is finally completed,the layout design of each module of the LDO circuit is analyzed in detail,and the layout implementation of the entire circuit are given.The overall layout area of the LDO is 409 μm*398 μm,and the chip was tested.The test results show that under the input voltage of 1.4 V～3.3 V,the output voltage of the LDO designed in this paper changes only 0.2 m V,and its linear adjustment rate is 0.0105%.When the load current changes from 200 μA to 100 m A,the output voltage only changes by29 μV,the load regulation rate is 0.29 m V/A.The PSR of the LDO is 88.5 d B at low frequency,and the PSR is 33.0 d B at 100 k Hz;the overshoot voltage of the LDO is 30 m V during transient response,and the response time is 10 μs,which meets the project index requirements.