Design Of A Low Quiescent Current Lowdropout Regulator

Today,with the rapid development of science and technology,people are increasingly demanding the integration of portable electronic products.Under the trend of miniaturization of electronic products,the chip area has been continuously reduced,and the working voltage of the chip has also been continuously reduced.As a key component of the power management chip,higher requirements have been put forward,so high-performance,low-power,high-stability power chips have always been an important direction for analog integrated circuit design.As a member of power management chips,low-dropout regulators have the advantages of simple structure,small size and low power consumption.They have been widely used in the industry and have important research significance.This article completes the design of a low-dropout linear regulator with low quiescent current and high power supply rejection ratio for the current market demand.In terms of reducing the quiescent current,this article starts from the quiescent current consumption of each part of the LDO to find out the main quiescent current part of the regulator,including the error amplifier,bandgap reference,and adjustment tube.In order to achieve low quiescent current characteristics,this paper designs a circuit to optimize the structure of the error amplifier and select a PMOS with a small quiescent current as the power tube to reduce quiescent current consumption.In order to improve the power supply rejection ratio,the feed-forward ripple elimination method is used to add a voltage close to the power supply ripple on the gate of the power tube,so that the power tube modulation voltage V_GS is protected from the power supply ripple noise to improve the power supply rejection ratio of the regulator.Finally,the specific circuit design of each module of the voltage regulator is completed,including:reference voltage source,bias circuit,error amplifier,protection circuit,enabling circuit and power tube.The low-dropout linear regulator designed in this paper with low quiescent current and high power supply rejection ratio is based on Huahong’s 0.18μm CMOS process.The regulator is simulated and verified in the Cadence software with the help of Hspice D simulation platform.The simulation results show that the voltage regulator outputs a stable voltage of 2.8V under the environment of–50℃～125℃,the input voltage range is 3.0V～5.5V,the maximum load current is 250m A,and the quiescent current can be as low as 12μA at no load.When the load is 20m A,the voltage regulator has 82d B power suppression ratio at 1k Hz and 60d B power suppression ratio at 100k Hz.In addition,the phase margin of the voltage regulator is relatively high under light load and heavy load conditions.The system has certain stability.The other performance parameters of the voltage regulator in the simulation results also meet the requirements and can meet the standards of this design.After completing the circuit design and verification of the voltage regulator chip,the layout design is carried out with the help of the Virtuoso layout design tool.In the design process,strictly abide by the layout design rules and process requirements,do a good job in matching key devices,and pay attention to latch-up effects and antenna effects.After the design is completed,DRC（design rule check）and LVS（comparison check of layout and circuit schematic）are performed on the layout,and the GDS II file is finally generated.