Research On Key Technology Of A High PSRR Capacitor-free LDO

With the progress of science and technology in the 21 th century,electronic equipment has seen substantially progress,gradually becoming an indispensable part of people’s daily life.In order to make electronic equipment work efficiently and well,a stable power supply is essential,therefore power management IC are becoming increasingly important.Low Dropout Regulator(LDO)is widely used in consumer electronics because of its simple circuit structure,low noise and low power consumption.With the rapid development of So C,capacitor-free LDO has attracted wide attention in the industry because it can work without external capacitor.Moreover,in highly integrated So C,the power supply ripple will have a great influence on the output due to parasitic capacitor coupling effect.Therefore,it is of practical significance to study the capacitor-free LDO with high PSRR.After a detailed analysis of the capacitor-free LDO,the zero-pole distribution before compensation is obtained.Based on adding a buffer stage between the output of the error amplifier and the gate of the PMOS power transistor to split one of high-frequency non-main poles into one with higher frequency so as to eliminate its influence on the stability of the system,a multi-stage Miller compensation structure with zero-adjusting resistors is used to change the pole distribution and generate zero points to compensate the circuit,so as to realize the stability of the capacitor-free LDO circuit.In order to give LDO high PSRR,the following two schemes are adopted: the PSRR of bandgap reference circuit is optimized through preset voltage regulation technology to offer the reference circuit with high PSRR,and transmit as little as power supply ripple to the input of LDO so as to improve the PSRR of LDO circuit.In order to realize LDO with high PSRR,the following two schemes are adopted: the PSRR of bandgap reference circuit is optimized through preset voltage regulation technology to offer the reference circuit with high PSRR,and transmit as little as power supply ripple to the input of LDO so as to improve the PSRR of LDO circuit.A high gain two-stage amplifier with a folded cascode structure as the first stage is used to further improve the PSRR of LDO circuit.In addition,in order to increase the reliability of the LDO circuit and protect the LDO circuit from being damaged in extreme cases,a protection circuit is designed.Considering the two extreme cases of excessive current and overtemperature of the circuit,current limiting and overtemperature protection circuits are designed respectively.Finally,A layout drawing of the completed circuit is made.Based on the SMIC0.13μm technology,the completed High PSRR capacitor-free LDO circuit is simulated and verified for important performance indicators under DC,AC and transient conditions.The results show that the LDO circuit can output stable voltage of 2.1V under the power supply voltage of 3 V,and can provide a maximum load current of 50 m A with the dropout voltage around 220 m V.The PSRR at low frequency is above 90 d B,and can still remain at about 55 d B at 1 KHz.Under different loads,the phase margin of the loop is higher than 60°,the system can run stably,and the quiescent current is lower than 500 μA.The design goal is met.After the circuit passes the performance verification,the circuit layout is drawn,and the parasitic parameters are extracted for post-simulation verification.The post-simulation results show that the LDO circuit has good performance.