Research On Verification Algorithm Of Electromigration Analysis For Advanced Integrated Circuit Technology Node

Integrated circuit is widely used in life,and the core of various electronic devices are integrated circuits.In some high-tech products,the role of integrated circuits is particularly critical,such as the AI chip that has received wide attention.Increased modernization has made Integrated circuits more and more important in human life.With the increasing complexity and integration of high-speed circuits,the increase in application fields,and the diversification of application environments,the reliability of integrated circuits has attracted more and more attention.After integrated circuit technology reaches the nanometer level,the current density increases sharply,the size decreases,and the operating frequency increases,making the electromigration on the wire one of the key issues affecting the reliability of integrated circuits.The current research on the reliability of electromigration on integrated circuits establishes a set of partial differential equations based on the extended Korhonen model.Then solving the PDEs by numerical solutions and analytic solutions.The study of these methods is mainly concerned with the balance between efficiency and accuracy.In this paper,an eigenfunction-based electromigration transient stress analysis method is proposed,to analysis the electromigration of power grid in the integrated circuit.The proposed method could solve the transient stress distribution on a general two-dimensional multi-segment interconnect tree,and sparse QR factorization method was used to calculate eigenfunctions corresponding to multifold eigenvalues.In consideration of the importance of eigenfunctions,this paper further proves the convergence of the proposed method,which can effectively reduce the terms of eigenfunction,which used in the stress calculation process,thereby improving the efficiency.Secondly,the proposed method can solve the transient stress problem under non-uniform current density distribution and non-uniform thermal effect distribution.For the irregularly shaped wires due to lithography process,the proposed method approximate calculate the transient stress distribution on the wires by correct the current density.Finally,the proposed method provides the analytical solution of the hydrostatic stress,based on the characteristics of the analytical solution,the bisection algorithm was used to find the void nucleation time of the power grid.The proposed method does not need spatial and temporal discretization,reducing the scale and times of the problems.In the experimental,the experimental sample selects the Power/Ground network benchmark provided by IBM.The accuracy of the proposed method is verified by comparing the relative error of the transient hydrostatic stress calculated by the proposed method and the finite difference method.Furthermore,the proposed method and the finite difference method was used to find the void nucleation time of IBMPG respectively,it is verified that the efficiency of the proposed method is three times faster than the finite difference method when the accuracy is enough.With the continuous expansion of the scale of integrated circuits,the scale of interconnect tree is becoming larger.The advantages of the proposed method will be more and more obvious.