Research On Avalanche Energy Of High Voltage Superjunction VDMOS

Power semiconductor switching devices,represented by vertical double-diffused metal oxide semiconductor field effect transistors(VDMOS),play an important role in electronic power systems.With the increasing awareness of environmental protection in the whole society,the power consumption and reliability of semiconductor switching devices are increasingly valued by designers and users.The superjunction VDMOS forms a superjunction structure by introducing alternating P/N pillars in the drift region of the traditional VDMOS,so that the device can increase the concentration of the drift region by an order of magnitude under the same breakdown voltage,thereby greatly reducing the specific on-resistance of superjunction VDMOS.So devices has lower conduction losses,at the expense of a more complex process.Semiconductor switching devices will be subjected to extreme high voltages and high currents at the same time in the process of Unclamped Inductive Switching(UIS),and the failure caused by this situation is an important failure mode of semiconductor switching devices.Avalanche energy used to evaluate the device's ability to withstand such extreme conditions.In this thesis,the current-voltage behavior of superjunction VDMOS in UIS process and the influencing factors of avalanche tolerance are studied through testing and simulation.A superjunction VDMOS with improved avalanche energy is proposed.The process flow is designed based on actual process conditions.The main contents of this thesis include the following aspects:(1)The principle of superjunction device is introduced,and the reason why the trade-off relationship between the breakdown voltage and specific on-resistance of superjunction VDMOS is better than that of conventional VDMOS is analyzed.The test circuit and test principle of avalanche energy are introduced,and the failure mechanism of conventional VDMOS in UIS process is analyzed.The junction termination technology of power devices is introduced,and the reasons why the conventional junction termination technology is not suitable for superjunction VDMOS are analyzed.The advantages and disadvantages of common processes of superjunction devices are compared,and the process flow of superjunction VDMOS is given.(2)A superjunction VDMOS avalanche energy test platform was built to test the avalanche energy of commercial devices.Combined with simulations,according to the current-voltage behavior of superjunction VDMOS in UIS process,the failure mechanism of superjunction VDMOS under UIS is analyzed,and the influence of process and external factors on device avalanche energy is explored.(3)A superjunction VDMOS with variable doping in the drift region is proposed,and its principle of improving avalanche energy is analyzed.The multiple epitaxial ion implantation process with high flexibility is selected,and a VDMOS with a breakdown voltage of 600V is designed by using the TCAD process simulation platform.The key parameters of cell and junction terminal are determined by process simulation.The basic characteristics of the device are simulated.The cell breakdown voltage of the device is698V,the specific on-resistance is 22.9m?cm~2,and the avalanche energy is improved by about 12%on the basis of the traditional superjunction VDMOS,which is 623.9m J.