Time-to-Digital Converter Based On Rotary Traveling Wave Oscillator

Time to digital converters(TDC)are used in the all-digital phase-locked loop(ADPLL)widely,regarded as the most important part.The conventional TDC used in phase-locked loop(PLL)faces the problem of poor phase noise.Meanwhile,the unified allocation mechanism of high-speed oscillation signal also needs further research.High-performance clock technology has made great progress currently.Due to its advantages of low skew and low jitter,the rotating traveling wave oscillator has attracted great attention.In addition,it is also a hot and difficult point to transform the high-speed oscillation signal of the rotating traveling wave oscillator(RTWO)into time information.The TDC is divided into two parts: the RTWO and the high-speed latch,and the basic principle of oscillator is introduced.The rotating traveling wave oscillator is composed of an oscillation circuit,a negative resistance compensation unit and an output buffer circuit.The oscillating circuit is a metal transmission line that is cross-connected end to end in a Mobius ring.The parasitic capacitance and inductance form an oscillating network.The negative resistance compensation unit adopts a cross-negative resistance controlled by a current source which can adjust the negative resistance.The output buffer contains a 12-bit tuning capacitor array,the lower 4 bits are fully customized MOM capacitors,and the upper8 bits are arrays formed by PMOS connecting like a capacitor.The NMOS switch control the capacitor connected in parallel to the resonant,the oscillation frequency of the oscillator can be tuned coarsely and finely.For the analysis of the traditional structure latch,the delay and offset voltage are reduced by increasing the discharge paths,and the kickback noise performance is optimized by adding a charge control pump under the tail current source.In addition,considering the influence of the PVT deviation,The capacitor in the charge pump is designed as a 4-bit MOM capacitor array.Then,the layout design of each circuit module is given.In order to avoid the latch transistor switching activities interfering with the operation of the oscillator,the latch layout needs to add a dummy cell controlled by the opposite polarity clock.It's necessary to design the matching clock tree and synchronous clock buffer to match the layout.When the clock tree passes through the transmission line and negative resistance unit area,the clock branch need to be shielded by metal connected to GND.The size of TDC core is 564?m×564?m,the size of TDC with connecting pins is 743?m×743?m.Finally,the simulation results show that the amplitude of stable oscillation is 300 m V,the tuning frequency range is 10.24-12.21 GHz,the lowest bit tuning accuracy is 78.8KHz,the tuning frequency variation of highest bit is 649.8MHz,and the phase noise range is-108 ?-120 d Bc/Hz@1MHz.The power of first order harmonic wave is 6.92 d Bm.The delay of proposed latch is 205 ps,the offset voltage is 0.578 m V,and the power consumption is247 ?W.Compared with the conventional latch,the kickback noise is reduced by about 5m V.The time precision of time to digital converter is ?/32,the range of time resolution is1.28-1.53 ps.