Research And Implementation Of Forward Error Correction Algorithm For Gigabit Ethernet Optical Transmission System

In the transmission process of optical network signals,long-distance transmission is a very important research direction.After long-distance transmission of optical signals,signal quality deteriorates,which leads to the reduction of optical SNR of output signals and the occurrence of error codes at the receiver.In order to improve the signal quality,erbium-doped fiber amplifier,Raman amplifier,remote pump and other equipment are generally added in the long distance transmission and the forward error correction code is added.Forward error correction codes can be used to improve the transmission distance of signals at a lower cost.The existing application environment of forward error correction codes is basically 2.5Gbit/s optical transmission network,but there is no appropriate forward error correction code to encode and decode gigabit Ethernet frames during transmission.At present,the forward error correction function is generally realized by using the mature IP core provided by foreign FPGA manufacturers,or special encoding and decoding devices abroad.Compared with special encoders and decoders,FPGA can provide forward error correction function with low cost.However,due to the slow start of domestic FPGA and the lack of encapsulated IP core on domestic FPGA,forward error correction codes are seldom applied in domestic FPGA platform.Based on the research of RS coding and decoding theory,this paper designs the RS coding and decoding device and the custom frame module based on domestic FPGA,and sets up the long distance transmission experiment system to test the designed program.The main contents of this paper are as follows:(1)Design RS(255,239)coder and decoder through the research of RS coding and decoding principle.Aiming at the problem that finite domain multiplication module consumes too much resources,a finite domain multiplier is implemented to improve the performance of multiplication module.The encoder module and decoder are implemented on FPGA.The encoder and decoder is tested on the designed FEC board.(2)To solve the problem of Ethernet message length,a custom frame design is proposed to adapt to RS codec.The self-defined frame module is realized based on domestic FPGA,and the program is simulated and debugged on board.Test the transmission effect of Ethernet data frames of different packet lengths,which can realize the slicing function of packets of variable length and the rate can reach 1.25Gbit/s.(3)The long-distance transmission experimental system was built to test the designed RS encoder and decoder and the custom frame packaging module.After analysis of the experimental results,the reception threshold of the long-distance transmission system using RS encoder and decoder and the custom package module was more than 5.5d B lower than that of the long-distance transmission experimental system without FEC function.