Efficient Algorithms And Hardware Implementations For 5G Polar Codes

The future communications pose a huge challenge of massive connections and ultra-high speed transmissions.However,with the background of Moore's law slowing down,the cooperative opti-mization and design between baseband signal processing and efficient hardware implementation are more important in the wireless communication.On the one hand,due to the trend of miniatur-ization and various sensors connected to wireless network,baseband signal processing systems are required to be designed by smaller area and power.On the other hand,as the current hardware process has approached the limit of silicon,baseband signal processing systems cannot get the direct improvement benefited from more advanced process.Two sides are both requiring the next gener-ation of mobile communication systems to optimize the software algorithms in terms of hardware implementation and achieve the well trade-off between performance and efficiency.Furthermore,compared with the analog RF front-end implementation,relatively little emphasis has been given to the practical design of digital baseband circuit.Generally,only combining between the research of digital signal processing and VLSI experience could exploit the potential of digital baseband systems.As one of key technology in 5G,polar codes are the core element to consist the 5G channel coding module.Hence,this dissertation has made a detailed research about polar codes for the cooperative optimization between advanced decoding algorithms and efficient hardware implementation.Since proposed in 2008,polar codes have become attracted widespread attention from academia and industry,which is the firstly proven to fully achieve the Shannon capacity on the binary discrete memoryless channel(BDMC).After merely several years,polar codes have been selected as 5G standards to take the responsibility to protect control channels in 5G e MBB scenarios.Among the various polar decoding algorithms,belief propagation(BP)decoding has several outstanding advantages,such as extremely high throughput,soft output and hardware-friendly feature,which proves that polar BP still has huge research and commercial value.This dissertation puts the main emphasis on improving the BP performance for 5G polar codes,making joint optimization between software and hardware,and proposing an efficient dedicated hardware which has been verified on ASIC platform.First,based on the analysis of message propagation process,this paper proposes a renew min-sum(RMS)decoding to accelerate the iteration convergence by renewing the R₀.For the early termination strategy,this paper presents a more efficient method by combining between G_Nand CRC,which could facilitate BP decoding to achieve better performance with less computational complexity.Based on the above optimization methods,this paper further modifies the conventional pipelined BPL decoding and proposes an EBPL decoding algorithm,which could decrease the ex-penses of the original Euclidean distance judgement.Numerical results show that the improvement gap could be 0.15 d B when L=8.The performance of belief propagation list(BPL)decoding is related to the selection of L factor graphs.Thanks to the analysis of loop construction on factor graphs,this paper proposes a method called loop simplification to select optimal factor graphs.Actually,some length-12 loops could be destroyed by redundant operations during message propagation process,and permuted factor graphs have different length-12 loops distribution.Hence,LS algorithm could achieve L optimal factor graphs based on the metric of the number of length-12 loops.Simulation results show that the performance improvement is 0.15 d B when frame error ratio(FER)is 10^-4,for(1024,512)codes with L=64.In addition,based on 5G polar construction,there is currently no method to design factor graphs targeted to specific errors.Then,this paper proposes the log-likelihood ratio(LLR)mean as the metric to measure bit reliability under BP decoding and re-defines the error-prone bit indices as the ones with smaller LLR mean.By swapping the error-prone bit indices to more reliable ones by bit-index permutation,this paper presents an improved factor graph set(IFGS)to design FGs targeted to specific errors.Numerical results show that the performance improvement of IFGS algorithm is 0.1 d B when FER is 10^-4and L=32,compared with LS algorithm.Based on 65 nm SIMC CMOS technology,this paper proposes the dedicated hardware imple-mentation for polar BPL decoder.In terms of inter-BP decoder,this work employs the state-of-the-art bidirectional double column structure and optimizes the original data flow,which saves almost half uniform routing structures in decoding process.Then,based on the cooperative optimization between the pipelined registers and folded memory,this work utilizes the pipelined registers to re-place the memory at the specific clocks,which could save 20%memory expenses.Besides,by fixing L list routings from the above IFGS into hardware in advance,this paper presents the fixed list routing structure to complete the permutations of input signals for different lists.Moreover,this paper employs a method to improve the timing schedule,which could pay only one extra clock to switch decoding lists.Based on ASIC synthesis results,the proposed polar BPL decoder with fixed list routing could achieve 5.07 Gbps for N=1024 polar codes when L=32 and E_b/N₀=4 d B.It is worth mentioning that the performance has exceeded that of CA-SCL and area is 3.362 mm².Furthermore,this paper makes an optimization for the proposed polar BPL decoder.Targeted to the drawbacks of fixed list routing circuit,we propose a design of flexible list routing generator.Based on the formula representation of bit-index permutation,this paper derives an uniform formula structure to decompose the list routings for all permuted factor graphs and proves that all list routing could be divided into the permutation and combination of n-1 sub-routing.Besides,the hardware design and numerical results are illustrated in this paper.