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Design Of 24.25?29.5GHz RF Switches Based On 65nm CMOS Process

Posted on:2022-01-28Degree:MasterType:Thesis
Country:ChinaCandidate:Y Z RenFull Text:PDF
GTID:2518306740996599Subject:Electronics and Communications Engineering
Abstract/Summary:PDF Full Text Request
RF single-pole-double-throw(SPDT)switch,whose performance directly affects the signal processing ability of the whole transceiver system,is a key module in the RF transceiver frontend system.With the continuous development of communication technology,the performance requirements of transceiver module in communication system are increasing,which puts forward higher requirements on the insertion loss(IL),isolation(ISO),and linearity of switches.Therefor,the research and design of high-performance RF SPDT switches has become one of the major difficulties in transceiver system design.Based on 65 nm CMOS process,this paper designs two types of 24.25?29.5GHz SPDT switches which apply to transceiver front end system.Because of the great difference between the transmitted power and the received power,both switches adopt an asymmetric structure to improve the linearity of the transmitter mode.Based on the symmetrical ?-type 50? matching structure,the first switch introduces shunt stacked transistors at the transmitting end to improve the linearity in transmitter mode,and uses a ?-type 50? matching structure in each branch for low-loss signal transmission.The second design,whose isolation performance is improved by LC parallel resonant networks,adopts an asymmetrical LC structure which removes the shunt MOS in the transmission branch and the series MOS in the receiving branch which are used in the symmetrical series-shunt structure to improve the linearity of transmitter mode.EM simulation shows that,in the frequency band of 24.25?29.5GHz,the first switch achieves insertion loss less than 1.75 dB,isolation greater than 24.32 dB,input 1dB compression point(27GHz)greater than 18.9dBm in the transmit mode,and insertion loss less than 2.135 dB,isolation greater than 18.02 dB,input 1dB compression point(27GHz)greater than 9.08 dBm in the receive mode.The second switch achieves insertion loss less than 1.61 dB,isolation greater than 24.3dB,input 1dB compression point(27GHz)greater than 37.89 dBm in the transmit mode,and insertion loss less than 1.47 dB,isolation greater than 16.7dB,input 1dB compression point(27GHz)greater than 9.92 dBm in the receive mode.Both RF switches have reached the design index requirements.The mixed simulation performance of the two CMOS RF switch circuits designed in this paper meets the system requirements and can be applied to the RF transceiver system of the corresponding frequency band.
Keywords/Search Tags:single-pole-double-throw switch, low insertion loss, high linearity, stacked transistor, asymmetric
PDF Full Text Request
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