Investigation Of The Gate Oscillation In SOI-LIGBT Under Short Circuit

As the core power device of the single-chip intelligent power module,the Silicon-On-Insulator Lateral Insulated Gate Bipolar Transistor(SOI-LIGBT)has received extensive attention due to its good integration and easy driving.The short-circuit capability of SOI-LIGBT device is one of the key factors that determine the reliability of single-chip intelligent power module.The short-circuit capability of SOI-LIGBT directly determines the reliability of the single-chip Intelligent Power Module.The high voltage and high current under the short circuit can easily make the internal electrical parameters of the device unstable,causing gate oscillation and even chip destruction.Therefore,it is of great significance to improve the short circuit oscillation characteristics of the device.The short-circuit oscillation characteristics of the SOI-LIGBT developed by our lab and CSMC Corporation have been studied in this thesis.It is found that the charge-field force caused by time-varying carrier density of the device can move the peak electric field on the surface of the device,which in turn continuously change the parasitic capacitance of the device's gate and eventually causes oscillation.Gate resistance and gate parasitic inductance will also significantly affect the short-circuit oscillation.In this thesis,two solutions are proposed:the P~+doping concentration of the collector is increased to improve hole injection;the P~+/N~+spacer structure of the emitter is used to reduce the accumulation of electrons in the emitter region.Both solutions improve the carrier distribution inside the device,optimize the electric field distribution,and eliminate the short-circuit oscillation phenomenon.The results show that:the breakdown voltages of devices with increased collector P+doping concentration and P~+/N~+spacing emitter structure are 583V and 585V,on-current density under standard conditions are 194A/cm~2 and 156A/cm~2,turn-off time are 108ns and 89ns.the short-circuit withstand time of the two schemes at 400V bus voltage are 8.7?s and 13?s respectively.At the same time,optimized devices can completely eliminate the gate voltage oscillation phenomenon existing in the traditional structure,and meet the expected requirements.