Integration And Implementation Of A Performance Evaluation Tool Based On Cache Subsystem Analitical Models

In the early stage of designing a processor architecture,the performance of the processor architecture is evaluated mainly through two methods: microarchitecture simulation and analytical modeling.The advantage of microarchitecture simulation lies in its high simulation accuracy,but due to its very slow simulation speed,it is difficult to be accepted in the early stage of processor design.Although the analytical modeling method is not as accurate as microarchitecture simulation,it is good for its evaluation speed and has been favored by the academic community.In order to improve the performance of the processor,the processor designers add the Cache subsystem between the processor core and the memory.Therefore,the accurate modeling of the Cache subsystem has an important impact on the performance evaluation of modern processors.In the work of the academic cirecle,although a large number of analytical modeling studies have been done on the processor Cache subsystem,these studies are usually focused on a certain performance index of the Cache,and have not formed a complete system framework.In addition,the analytical modeling of Cache subsystem in related papers is not open source.Thirdly,from the perspective of application,the existing analytical model is difficult to use because it is not integrated and does not provide a user-friendly interface.Therefore,this paper integrates and implements a tool to evaluate the architecture of the processor Cache subsystem based on the previous research on the analytical modeling of the processor Cache storage subsystem in the laboratory.For a given hardware architecture configuration,the tool can quickly obtain relevant performance indicators to help designers explore the design space.The C-PET developed in this thesis is all written in Java language.First,the software trace information obtained by Gem5 is installed into a standard format file.Secondly,using the object-oriented design idea,the single-level Cache miss rate model,the downstream Cache behavior model,the multi-core shared Cache behavior model and MLP model are encapsulated in the object to form the model module.In addition,C-PET will provide the user with a graphical interface and a visual display of the model output.Finally,C-PET leaves a variety of interfaces in the design process to facilitate more functional expansion and model integration.Compared with Gem5,the average error of C-PET in predicting the downstream Cache miss rate is less than 5%,the average error of multi-core shared Cache miss rate is less than 5%,and the average error of predicting MLP is less than 8%,average evaluation speed is increased by two orders of magnitude.