Research On Processor's Analytical Model Of Performance

With the increasing performance of modern superscalar processor, processor architecture is becoming more and more complex and much more difficult to evaluate. Simulation with its flexiblity and its accuracy on evaluation of the overall performance has been the primary tool for processor performance evaluation, but it is very time-consuming, and provides little insight into the various factors that determine the overall performance. Therefore, it is very important to establish a rapid, relatively accurate model which can complete the task.Based on interval analysis, this paper achieved an analysis model of balanced superscalar processor performance. This model studies on the the behavior of instruction dispatch, and divides total execution time of processor into isolated intervals by missed events. And each interval includs the time for executing useful instruction and the time for handling miss event. It shows the performance in the way of CPI stacks. This model only needs parameters of processor configuration, application-related characteristics and the characteristics that dependent on both the application and processor configuration to analysis performance.The later two parameters can be quickly got from functional simulator. We analyse four balanced out of order superscalar processor with bandwidth of 2,4,6,8, and compared with the M5 simulator which is cycle-accurate , the average CPI error for SPEC CPU2000 integer programs were 7.89%,8.9%,9.46%,10.9%. Experimental results show that the model is fast and accurate in a certain range. It can provide more insight into how the processor configuration and the program characteristics impact the overall performance. According to the model's error analysis, the model's error stems from neglet of the overlaps between front-end and back-end and the rough evaluation for the penalty of each miss event. The maximum error of the model stems from the rough evaluation for instruction Cache miss penalty. In view of this, we first analyzed what are the front-end factors that have impact on the average penalty of level 1 instruction Cache using interval analysis model, and validate the analytical results through simulation experiments. Our study shows that all of those like lower-level storage system access time, fetch bandwidth, fetch queue size, level 1 instruction Cache miss rate and the program characteristic will have impact on the average of level instruction Cache miss penalty.