Design Of Multichannel Programmable Gain Amplifier With Wide Gain Adjustment Range

For the bioelectronic signal processing system,because the bioelectronic signal amplitude changes greatly and there are various non-ideal effects in the propagation path,the variable gain amplifier is often needed to process the input signal to ensure that the proceding stage circuit can receive the signal with stable amplitude.And with the rapid development of digital signal processing technology,programmable gain amplifier controlled by digital signal has gradually replaced variable gain amplifier in many applications,which has a good application prospect.In this thesis,the multichannel programmable gain amplifier with wide gain adjustment range in bioelectronic signal processing is designed and studied.The programmable gain amplifier has 16 independent signal processing channels.For each signal processing channel,in order to meet the requirements of wide gain adjustment range,the cascade mode of coarse and fine gain stages is adopted.The coarse gain stage takes 16 d B as the step size and provides a gain adjustment range of-64?48d B.In structure,it is divided into amplification part and attenuation part,which is composed of two parallel branches providing positive gain and negative gain respectively.The amplification part and attenuation part are cascaded with fixed gain amplifiers,and there are four cascades at most.The fixed gain amplifier uses transconductance enhanced source degradation amplifier to improve the linearity.A resistor closed-loop negative feedback structure is used in the fine gain stage,and a two-stage folded cascode structure is used in the OP amplifier,which covers the gain adjustment range of0?15.5db in 0.5d B steps.In order to simplify the control mode,the serial control code is used to set the gain of each channel.The gain control logic mainly includes output register gating module,16-bit shift register,output register array,switch decoding logic and other parts.It has three input terminals: CLK,RST and DATA.According to the serial control code received by the DATA terminal,the gain of each signal processing channel is set,which improves the flexibility of control.In this thesis,the schematic design and layout design of the whole circuit are completed in TSMC 0.18?m CMOS process,and the pre and post simulation are carried out.The area of the circuit layout is 1.2mm×1.05 mm.The simulation results show that the gain adjustment range of the circuit is-63.5?63.79 d B,and the 0.5d B step value control is realized.The 3rd order input intercept point is 5.14 d Bm,the equivalent input noise is 7.56?V in the bandwidth of 10?30k Hz,and the single channel current consumption is 2.15 m A,which can meet the index requirements.