Research And Design Of Wide Dynamic Range And Accurate Gain Control Programmable Gain Amplifier

With the rapid development of wireless communication technology, modern wireless communication systems need to be compatible with different bands and different modem mode, so that more and more researchers paid attention to multi-band multi-mode wireless receiver. For the consideration of base station construction costs, as well as communication speed, communication quality and the reliability of the information exchange in different applications, the multi-band multi-mode receivers based on the typical structure of zero-IF receiver are becoming hot spots and focus of wireless communication system research. As the key modules in the baseband circuitry of zero-IF receiver, the programmable gain amplifier(PGA) plays an important role in the dynamic range, reception sensitivity and other key performance of entire radio receiver system.For the application of zero-IF receiver, this paper designed a high-performance, wide dynamic range and accurate gain control programmable gain amplifier chip, which includes the programmable gain amplifier core module, digital decoder circuit and the DC offset cancellation loop module. This paper proposed a novel current-mode instrumentation amplifier architecture based on a core CCⅡ unit and an accurate gain control mode based on a novel programmable current mirror, composing the programmable gain amplifier core module. The proposed architecture increases the gain-bandwidth product and gain stability by increasing the current transmission coefficient of current-mode instrumentation amplifier. Also, through the mixing gain adjustment method combining a constant current density bias programmable current mirror and a resistance ratio array, the PGA can further improve the gain accuracy, reduce the number of program-controlled switches, simplify the decoder circuitry which lowers the complexity of overall programmable gain amplifier circuit, improve the stability of the system and achieves an accurate gain control over a wide dynamic range.In this paper, the proposed programmable gain amplifier was implemented and verified with 0.18μm CMOS. Post layout simulation results show that the system chip area is 727μm* 717.6μm; the total power consumption is 3.22 mW with a supply voltage of 1.8V; the gain dynamic range varies from 0 to 63 dB with a 1dB stepping gain; the gain error is less than ± 0.2dB; the minimum-3dB bandwidth is 27.85MHz; the input equivalent noise is 10.05 nV / (?) at 32 dB and 5MHz; the input third-order intercept point varies from-6.75 dBm to 5.05 dBm. The proposed programmable gain amplifier chip can achieve digital programmable gain amplifying for the zero-IF signal after frequency conversion with zero-IF wireless receiver digital baseband.