Analysis And Design Of Post-Processing LDPC Decoders For Lowering Error Floor

LDPC(Low Density Parity-Check)codes,as a common method of channel coding,is widely used in many communication systems.However,there is the problem of error floor in the iterative decoding of LDPC codes,which causes great trouble in some special application scenarios of LDPC codes.It has been proven that trapping sets are closely associated with error floor,and the post-processing methods can deal with the trapping sets to lower the error floor.In this paper,some common trapping sets are analyzed,and a post-processing method based on iterative marking is proposed,which can find error bits effectively to improve the performance of LDPC codes in the error floor region.And in order to reduce the computational complexity and the difficulty of hardware design,this paper also proposes a simplified method of iterative marking post-processing method,in which different improvements are made for codes with different construction to get better performance,and some simulation experiments are carried out to prove the effectiveness of proposed method.As for hardware design of post-processing decoder,this paper,based on the BlockSerial Layered architecture of LDPC codes,takes(2304,1152)codes in IEEE 802.16 e standard as an example to implement the simplified iterative marking post-processing method.The decoder divides VNU into two sub-modules to process the two lines of the matrix at the same time.And in this decoder,some optimization methods are used to avoid excessive consumption and read-write conflicts in the storage arrangement.Early Termination module is also applied to finish decoding in time.In the final implementation based on FPGA,the post-processing module occupies only 8.3% of the lookup table resources and very few register resources.