Research And Implementation Of Acceleration Of Binary Convolutional Neural Network Based On FPGA

In recent years,with the large-scale application of artificial intelligence in life and production,deep learning algorithms have also attracted more and more researchers' attention.As a widely used algorithm in deep learning,convolutional neural network has achieved good results in many fields.However,as the network scale gradually increases,the corresponding calculation amount also increases rapidly,which limits the application scenarios of the network model.At present,the mainstream neural network deployment platforms are mainly CPU and GPU,but these two platforms have high power consumption and large device size,so they cannot be deployed in some mobile application scenarios with power consumption constraints.The binarized convolutional neural network quantizes the weights to +1or-1,which avoids the multiplication operation during calculation,and only requires1 bit to store the binarized weights,which effectively reduces the storage space requirements.FPGA field programmable gate array is a kind of computing equipment with rich logic and computing resources,high parallelism,flexible and configurable characteristics.It is very suitable as a deployment platform for binary convolutional neural networks.Based on the FPGA platform,this paper studies the acceleration of the forward computing process of the binarized convolutional neural network.Firstly,the principle and model structure characteristics of the convolutional neural network are studied,and the expression of the network model on the hardware after binarization is analyzed.Efficiency,effectively reducing the use of multipliers in hardware implementation.According to the calculation characteristics of each layer in the network model and the parallelism in the forward calculation process of the network,the parallel accelerated calculation module of the network model is designed by pipeline method,including convolution layer module,pooling layer module,activation function and full connection.layer module.Among them,in the data buffering method,this paper improves the line buffering method used by the traditional convolutional layer and pooling layer,and reduces the usage of register resources required for data buffering.In terms of implementation,it is mainly realized in RTL mode,and is compiled in Quartus ? software to complete the hardware circuit design of the algorithm as a whole.Finally,experiments are carried out on the DE2-115 FPGA development board of Altera Corporation,which proves the effectiveness of the designed acceleration system.The experimental results show that when the method in this paper is used to perform the classification task of the CIFAR-10 dataset,the recognition speed is 1.47 times higher than that of the CPU platform,and the maximum error is controlled at0.051.