Optimal And Design Of Convolutional Neural Network Based On Processing In Memory

Convolutional neural network(CNN)is widely used in the fields of computer vision and artificial intelligence.With the advent of the era of big data,the traditional von Neumann computer architecture storage wall problem has become more and more serious,and it has been unable to meet the data processing needs of convolutional neural networks.Processing in memory(PIM)architecture,as an emerging technology,provides a new computer architecture that supports data operations in memory,reduces the number of times the processor accesses the memory,and increases data processing parallelism and data processing speed.With the emergence of a large number of emerging non-volatile memory(e NVM),PIM architecture has a diversified choice of storage media.For example,spin transfer torque magnetic random access memory(STT-MRAM)is close to traditional dynamic random access memory in read and write performance,and its capacity,energy consumption and price are significantly better than dynamic random access memory,Has become a competitive storage technology.This thesis mainly completes the optimization design of convolutional neural network based on STT-MRAM in-memory computing architecture.In order to realize the processing in memory of the convolutional neural network,this thesis proposes a new memory computing architecture based on STT-MRAM,and designs two memory computing architectures based on static random access memory(SRAM)and ferroelectric field effect transistors(Fe FET)for comparison and analysis.First,research and study of STT-MRAM related technology and characteristics,then compare and analyze the structural characteristics of SRAM and Fe FET.The design implements the STT-MRAMbased adder design and Kirchhoff's law-based vector matrix multiplication,and the vector multiplication matrix operation is directly implemented on the memory array.This thesis is designed from the bottom up from the chip level,the circuit level and the algorithm level,and finally constitutes a new memory computing architecture.At the chip level,a layout algorithm is proposed to optimize the layout of the convolutional neural network in the memory computing architecture,and the weight mapping method as well as the data flow and pipeline system are optimized.At the circuit level,three parallel synaptic arrays based on different memories are implemented,and three transposed synaptic arrays are implemented based on their optimization,and the weight gradient calculation unit is implemented by combining the adder and the vector matrix multiplication cross array.At the algorithm level,the inference accuracy and training accuracy of the convolutional neural network in the memory computing architecture of this paper are estimated.In order to verify the optimization effect of the designed STT-MRAM-based memory computing architecture on the convolutional neural network,the circuit-level indicators and the overall architecture indicators were compared with the SRAM-based memory computing architecture and the Fe FET-based memory computing architecture.The experimental results show that the performance of the convolutional neural network based on the STT-MRAM-based memory computing architecture designed in this thesis is better than the other two memory computing architectures,both at the circuit level and the overall architecture.It is better than pure GPU architecture in terms of total time,accuracy and average loss.Compared with the SRAM-based memory computing architecture,the synapse array area,neuron area,and total area are optimized by 81.38%,68.16%,and79.90%,respectively,and the overall leakage power consumption is optimized by about 90%.Compared with the Fe FET-based memory computing architecture,the synaptic array area and total area are optimized by 78.62% and 74.62%,respectively,and the performance in terms of neuron area and leakage power consumption is basically the same.Compared with the traditional GPU-only architecture,the STT-MRAM-based memory computing architecture is optimized by 52.99%,3%,and 13.5% in total time,accuracy,and average loss,respectively,which is slightly better than the other two memory computing architectures.