Research And Implementation Of APB-SPI Verification IP Based On UVM

With the continuous advancement of integrated circuit process technology and SoC systemon-chip design technology,the scale and complexity of integrated circuit chip design continue to grow.In the current SoC design flow that can reuse a large amount of IP,the time spent on functional verification in the entire chip design cycle has reached 85% or more.Verification IP can automatically generate test stimulus,data comparison and coverage statistics and other functions,and its verification components can also be well integrated and reused in the SoC system-level verification environment.Therefore,the development of verification IP can improve the verification efficiency of SoC and reduce the workload of verification personnel,which has great research value.The verification method has undergone the development of verification methodologies such as e RAM,RVM,VMM,OVM,etc.from the traditional directional test method.Finally,the official EDA organization united the three major EDA companies of Synoposys,Mentor and Candence,and combined the advantages of the verification methodologies in 2010.Launched the UVM verification methodology based on the System Verilog verification language.Follow-up has also been launching new versions and adding new functions,which are widely used in the integrated circuit industry.In addition,SPI(Serial Peripheral Interface)serial low-speed peripheral device interface is the most widely used standard interface protocol in the world.Research on the APB-SPI verification IP has strong practicability.This thesis takes the APB-SPI controller as the research object and uses UVM verification methodology to build its verification IP.The main work is as follows:(1)Completed the in-depth study of the APB-SPI controller module and analyzed its functional attributes to decompose the functional test points of the design under test.It is necessary to complete the APB bus and SPI interface timing check of the DUT,whether the APB bus can access the internal registers correctly,the serial data receiving and sending function of the SPI port in all functional mode configurations,the frequency division function and CRC in the SPI master mode Check the check function.Insert functional coverage into the conditional branch of the verification code,collect the operation status of each branch,and measure the completeness of the verification work with the functional coverage group and code coverage.(2)Completed the development of the UVM verification platform for the APB-SPI controller module.Based on the verification plan,the overall architecture of the UVM verification platform was designed and implemented.The specific verification components include the driver,monitor and sequencer components integrated in the APB master agent,the driver,monitor and sequencer components integrated in the SPI master/slave agent,and the register model component.,Scoreboard components and environment components,through TLM to achieve communication between components.The DPI-C interface is used to connect the scoreboard verification component and the C code of the external CRC algorithm,and the joint simulation of the UVM verification platform and the C code is realized.Write a python script to insert functional coverage into the conditional branch of the verification code.(3)The function test and test result analysis of the APB-SPI controller module have been completed.According to the functional test points decomposed by the verification plan,we wrote spi base test,apb2 spi reg test,spi data transfer test,spi master div dheck test and spi crc check test,as well as supplementary test cases for the functional points that are difficult to cover in the test,and run After passing,a regression test is performed.Finally,the coverage rate was collected.The overall code coverage rate reached 97.26%,and the function coverage rate reached 100%,which met the verification requirements.This paper uses the UVM verification methodology based on System Verilog language to build a module-level verification environment,and realizes the characteristics of random testing with constraints,reusability of verification components,automatic comparison function,coverage collection function and automatic operation of scripts.The VCS simulation tool under the linux environment performs simulation and completes the functional verification of the design under test.