Demosaic Algorithm And Hardware Implementation In Image Signal Processing

With the expansion of the application scope of digital imaging technology,Requirements of the market for image clarity and reduction is higher and higher.As one of the core technologies in digital imaging systems,demosaicing technology has received extensive attention.How to improve the quality of the image reconstructed by the demosaicing technique,and reduce the error color,and implement the demosaicing algorithm better with hardware has become the focus of everyone's attention.This topic is the actual project engineering of the enterprise,which researches a high-performance demosaicing algorithm based on constant color difference and gradient,and implements this algorithm in hardware.The main contents of the research project are as follows:(1)Evaluate the processing results of different algorithms for the same Bayer format image,and compare the performance of the algorithms.This article describes the specific calculation methods of the bilinear interpolation algorithm,the color smoothing interpolation algorithm and the improved demosaicing algorithm.The peak signal-to-noise ratio(PSNR)of the images processed by the three algorithms are calculated respectively to be 20.09d B,33.24 d B,and 43.79 d B.It can be seen that the PSNR value of the improved demosaicing algorithm is much higher than the other two algorithms.From the three images obtained,it can be seen that the quality of the image reconstructed by the improved demosaicing algorithm is obviously higher than the other two groups of images.And there are almost no wrong interpolation colors in the image.(2)Propose a design plan and draw a hardware system frame diagram.According to the improved demosaicing algorithm,the design scheme of the entire hardware system is proposed.The functional modules in the algorithm are divided,and the hardware system frame diagram is drawn.(3)Use the verilog hardware language to write code.First,using verilog hardware language describe the top-level interface and the interfaces of each module according to the drawn hardware system frame diagram,and connect the instantiated modules in the top-level module,and describe the circuit design in each module.(4)Modificate and improve the code.After the entire hardware system is described in verilog hardware language,using vcs and verdi tools compile and simulate the code,and modify the grammatical errors.And after the code is compiled,perform behavioral functional verification for different functional points of the module design,and compare the output results of the algorithm model and the hardware system with the same incentives.find errors in the entire design and modify it,repeat the above process until the algorithm model is exactly the same as the output result of the designed hardware system.(5)Results analysis.The completed hardware code is integrated into a gate-level netlist in the TSMC tt12nm process library,and the synthesized area report and timing report are obtained.The area of the entire hardware system is 51534?m~2.The clock frequency is666MHz.The entire hardware system meets the timing requirements.Finally,bayer format image which was shot specially and suitable for demosaicing is used as the input of the entire hardware design,and the processed two sets of pictures are obtained.The processed color image has clear pixels and full tones.In summary,The entire hardware system consumes less hardware resources,and has faster data processing speed and excellent performance.