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Design And Verification Of Digital Image Demosaicing IP

Posted on:2014-08-09Degree:MasterType:Thesis
Country:ChinaCandidate:Y B WangFull Text:PDF
GTID:2268330401453843Subject:Software engineering
Abstract/Summary:PDF Full Text Request
Imaging technology is the key part of the digital image acquisition system, usuallymanufacturers only using a single charge-coupled device (CCD) or complementarymetal-oxide semiconductor (CMOS) sensor for lower production costs and smaller chiparea. For using only one sensor, it must to be covered with a layer of color filter array(CFA) coating on the surface of the sensor. And Bayer CFA is the most widely usedtoday. The original data for each pixel only contains information about one color.However, information for all three primary colors is needed at each pixel to reconstructa color image. Some of the missing information can be recreated from the informationavailable in neighboring pixels. This process of recreating the missing color informationis called color interpolation or demosaicing. This paper introduced the current mostpopular demosaicing method in detail, such as the bilinear interpolation and thedirectionally weighted gradient based interpolation and then make a comparison withMatlab. Considering to the requirment of demosaicing effect and hardware real-timeoperation, we proposed an improved bilinear interpolation method, and designed an IPcore. After EDA simulation and FPGA test, the IP core can basically meet the designrequirements.The algorithm used here combines the bilinear interpolation, the directionallyweighted gradient based interpolation and the algorithm based on consant-hue rule. Itachieved good results by using bilinear interpolation method and gradient methodrespectively to recover the green component and using the algorithm based onconsant-hue rule to recover the other two color components. At last, executed EDAsimulation of the IP core with Modelsim. In function simulation, Mixed simulation wasused here to improve the simulation efficiency. The IP has been verified by FPGA in35series board of Hisilicon, meet the design requirements basically. In FPGA verification,proposed a field recovery method for fast positioning, which has a great guidingsignificance.
Keywords/Search Tags:BAYER, DEMOSAICING, IP
PDF Full Text Request
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