Research On Joint Fault Location Technology Of Software Parameter Value And Time Sequence

Combinatorial testing is an effective method to achieve high test coverage.It can achieve high test coverage with as few test cases as possible.In combinatorial testing,when the running results of some test case sets are known,how to quickly and effectively locate faults according to the test cases that cause system faults is an important problem,The research on fast fault location technology of combinatorial testing can help testers to find the source of fault and correct it effectively to improve the system under test.The input of embedded software has the characteristics of time sequence,including the order of input parameters and the injection time of parameters.The injection time includes the order of input,and the input order only considers the order of time,so the demand of time sequence is lower,while the injection time is more complex,and the demand of time sequence is higher.Aiming at the time sequence characteristics of input parameter injection,this paper proposes a fault location algorithm based on joint coverage array of value and time.Aiming at the problem of prioritizing large-scale joint coverage arrays,a test case set prioritization method based on machine learning is proposed.It provides basic guarantee for high reliability verification of real-time embedded system.Aiming at the fault location of time sequence test cases of embedded software system with the requirements of joint coverage of value and tim e,a fault location algorithm for joint coverage array of value and time is proposed.Through the calculation of index pseudo security value group,the uncertain interaction set is determined,and the adaptive replacement strategy is used to generate addit ional test cases.The index security value group is generated by iterative calculation for many times,and the joint fault location of value and time joint array is realized.When the joint coverage array is large in scale and the test cost is limited,it is difficult to run all the test case sets.This paper designs a fault location algorithm for part of the test case sets with partial test results.For the value combination fault,the correct case that meets the specific standard is selected as the locati on case set,The cycle accumulation replacement strategy is used to locate the left and right fault factors;For joint faults,the fault types contained in the fault test cases are classified firstly.According to the value and time combination faults,the partial cycle accumulation replacement strategy is adopted,and the index value cycle accumulation replacement strategy is implemented for joint faults to realize the fault location of part of the test case set.For large-scale test coverage array,it will take a lot of time and cost to execute.In order to select the test case set that can guarantee higher fault detection rate under limited test cost.In this paper,a test case prioritization method based on support vector machine is proposed.Firstly,support vector machine is used to train the test results of a low strength coverage array,and a high strength coverage array with the same input parameters is predicted according to the training results.Secondly,a small part of the test results of the high strength coverage array is trained,and the rest of the coverage group is predicted.The test cases in the coverage array are sorted according to the prediction results.The test cases that will lead to the failure of the system under test are sorted in advance.Selecting subsets from the ordered coverage array after sorting can reasonably replace the whole coverage array and save testing cost.On this basis,an iterative learning iterative classification sorting method is proposed,and the results show t hat the generated ordered covering array subset can cover more faults interactions.Based on the above algorithm,a fault location tool is developed,which can realize joint fault location and fault location of partial test case sets.A high coverage platform of complex embedded software is built to verify the effectiveness of this algorithm in the actual hardware in the loop simulation system.