Study And FPGA Implementation Of Handwritten Letters Recognition Based On Convolutional Neural Network

Deep learning provides an efficient method for machines to solve complex problems,and is widely used in pattern recognition,automatic control,signal processing and other fields.Although the Convolutional Neural Networks(CNNs)included in deep learning have powerful performance,as the depth of the CNNs continues to expand,problems such as complex network levels,huge amounts of data,and intensive data storage have appeared,which may restrict the application of convolutional neural networks in embedded systems.The programmability of FPGA shortens the design time and facilitates later maintenance.Its parallelism makes the circuit run faster and has a higher bandwidth,which can meet the requirements of convolutional neural networks for data parallel processing.With the development of the industry,FPGA on-board resources have become more abundant,making it a good platform for building and running convolutional neural networks.In this thesis,a system based on the CNN is built to recognize 26 handwritten capital letters in real time with Cyclone IV series development board.The research contents are as follows:(1)Establish a handwritten letters data set.Collected and screened out 213,962 pictures of handwritten letters that conform to the writing habits of Chinese people.And the image data is converted into a format consistent with the MNIST data set.The training set contains 148,224 pictures and the test set contains 65,738 pictures.(2)A 10-layer lightweight convolutional neural network is proposed,which can reduce a large number of model parameters.Compared with the Le Net-5 model,the number of parameters of the proposed model is reduced by 90%.And the test accuracy rate of the proposed model is 94.41%.Experiments show that this design has significant advantages compared with other recent literatures.(3)Fixed-point processing of data.Since the floating-point operations implemented on FPGA needs to consume a lot of on-chip resources,floating-point numbers are converted into fixed-point integers.By comparing the recognition results before and after the fixed-point processing,it is determined that the minimum number of bits for this processing is 12(not including the sign bit).(4)The recognition system implemented on FPGA takes 237,626 clock cycles to complete the recognition of a single frame image.Under the 50 MHz operating frequency,the recognition rate is 4.75 ms per frame.The number of logical resources consumed by the entire system is 7,273(33%),and the number of storage resources consumed is 454,326(75%).