| Convolution Neural Networks(CNN)are often used in the field of artificial intelligence vision.In recent years,with the popularity of deep learning,convolutional neural networks have also been widely used in aerospace and other fields in scenes such as target detection and recognition.Most convolutional neural networks basically run in a GPU environment.GPU can realize real-time processing,but its high-power consumption and high-cost make it very difficult to meet the application requirements of some low-power and low-cost embedded scenes.Therefore,it is very meaningful to develop a set of convolutional neural network accelerator with high calculation speed,high accuracy and low power consumption.The following is the specific research content:(1)The calculation principle of convolutional neural network and the related principle of hardware acceleration are deeply studied,and the fixed-point quantization is carried out for the typical handwritten digital recognition network model,so as to effectively reduce the calculation amount of network model parameters.(2)Based on the idea of software hardware cooperation,convolution circuit and pooling operation circuit are designed by HLS.Based on the design idea of FPGA,the convolution circuit was decomposed in operation space,optimized in interface and optimized in cycle by using HLS tool,and optimized in interface and optimized in cycle for pooling circuit.The interface scheme of the accelerator circuit is optimized and configurable convolutional accelerator circuit and pooled accelerator circuit are finally generated.(3)Through the framework construction of PYNQ,the test scheme of the accelerator is designed.According to the designed accelerator,the test process of hardware layer,software layer and application layer is designed successively.Aiming at the typical handwritten digital recognition network,a test system was built under the development environment of PYNQ-Z2 to test and verify the performance parameters of the accelerator.The final test results show that the computational speed of the convolutional neural network accelerator designed in this paper reaches 37.63 FPS when testing the MNIST dataset.Compared with the ARM processor of the PYNQ-Z2 embedded platform,the accelerator designed in this paper achieves 42.1 times the acceleration effect.The recognition accuracy is more than 98%.The average power consumption is about 1.825 W,and the power efficiency is 20.62frames/J,which fully meets the requirements of low power design.The convolutional neural network accelerator designed in this paper based on the PYNQ embedded platform has excellent performance in terms of acceleration effect,power consumption and configuration flexibility,and it is convenient to transplant and has high application and promotion value. |
