Energy-efficient Integrated Circuit Design For Continuous Intelligent Perception Applications

The intelligent Internet of things is becoming more and more popular in people’s life and production activities,followed by its massive data.How to efficiently store,transmit and process these data is a problem that must be solved in the process of the further popularization of the Internet of things.It is a feasible solution to make the terminal have the ability of local data processing by decentralizing the computing power to the edge of the system.However,in the traditional perception system,limited by the von Neumann architecture,"power wall" and "memory wall" always exist.At the same time,the deployment of neural network on the terminal,such as computing intensive algorithms,further aggravates the energy consumption bottleneck.By integrating intelligent processing module at the sensor,the continuous intelligent perception system realizes the local intelligent processing of data,thus reducing the amount of data conversion and transmission,further alleviating the computational pressure of the post system.This method can effectively overcome the above energy consumption bottleneck.Therefore,this paper studies the design of high-efficiency integrated circuit in continuous perception system,and designs a chip for continuous intelligent perception applications.The main work of this paper is as follows:(1)A kind of computing-in-memory unit(CIM unit)is designed.The unit can be used as a standard SRAM memory,at the same time,multiplication operation can be carried out in the unit.On the basis of CIM cell,it is expanded horizontally and vertically to form CIM cell array.Since the array supports the current mode addition,it has the ability to perform multiplication and accumulation(MAC)efficiently.At the same time,it supports the mapping of neural network algorithm.(2)The system architecture based on CIM unit is designed.The architecture adopts mixed signal mode,including digital logic control module and corresponding supporting circuit,which enables CIM cell array to carry out storage operation and calculation operation respectively under appropriate logic control,while giving consideration to high energy efficiency and expansibility.(3)For the above-mentioned circuits and architecture design,sufficient circuit simulation and verification have been carried out,including analog circuit design and simulation,digital module coding and debugging,mixed-signal simulation and back-end verification(LVS and DRC).On this basis,the tapeout verification under the TSMC 65 nm process node was carried out.(4)For this chip,a reasonable test scheme is developed,and the necessary auxiliary circuits are designed to form a chip centered computing platform to complete its functional test and power consumption analysis.The energy efficiency of the chip can reach 15.75TOPS/W.Furthermore,a wake-up system is designed to verify the effectiveness of the chip.The results show that it can achieve 93.0% keyword recognition accuracy and 98.0% face detection accuracy.