Research And Design Of Low Power SAR ADC With Adaptive Sampling Rate

In recent years,with the enhancement of personal health awareness,biomedical signal acquisition chip has attracted great attention and become a research hotspot in the field of integrated circuits.As the core module,analog-to-digital converter(ADC)plays a key role in the performance of the acquisition chip.Successive approximation register(SAR)ADC has the advantages of low power consumption and many digital modules,so it is very suitable for the system.Therefore,this thesis designs a 12-bit low power SAR ADC with adaptive sampling rate for biomedical signals.The amplitude of biomedical signal changes slowly for a long time and sparsely.Traditional Nyquist ADC has waste of power consumption and redundancy of data.In this thesis,the difference between the two sampling voltages is detected by delaying the reset time of the upper plate to judge the change speed of the signal.Then the sampling rate can be switched adaptively,which can greatly reduce the power consumption and the amount of data.The designed SAR ADC mainly includes digital to analog converter(DAC),comparator and sampling-hold module.The DAC adopts a segmented capacitor array with redundant bit,and the improved monotonic switching scheme is used to reduce the common mode voltage drift and the power consumption;the two-stage full dynamic comparator composed of complementary input pairs is adopted to reduce its noise and power consumption;the gate voltage bootstrap switch in the sample hold circuit increases stack transistors and virtual transistors to improve sampling accuracy.In addition,aiming at the parasitic capacitance and mismatch for DAC layout,this thesis studies a digital foreground calibration scheme,and a behavior level model is established by using MATLAB.The circuit schematic and layout are designed in 0.18 ?m CMOS process.The core area of the layout is 250 ?m*350 ?m.The post simulation results show that the power consumption of the SAR ADC is only 4.65 ?W at a sampling rate of 120 k S/s and a supply voltage of 1 V,the spurious free dynamic range(SFDR)is 76.29 d B,the signal to noise and distortion ratio(SNDR)is 68.94 d B,the figure of merit(FOM)is 16.9 f J/conversion step,and the effective number of bits(ENOB)is 11.16 bit.The ENOB reaches 11.96 bit after calibration,which is improved by 0.8 bit.