Parallel Fault Simulation On Multi-core CPU

Testing has been considered to be one of the most critical links in the whole process of commercial integrated circuit design and manufacturing.With the rapid development of semiconductor manufacturing technology,the size of the circuit decreases and the integration and complexity of the circuit grows,which leads to the explosive increase of test data and test time,and the rapid increase of test cost.The research of integrated circuit testing becomes more and more important.In digital integrated circuit testing,fault simulation technique is the simulation for fault model.Fault simulation is crucial for test generation,test design and reliability evaluation of integrated circuits,so studying how to accelerate the fault simulation of logic circuits is of great significance to integrated circuit.The research on logic circuit fault simulation traditionally focuses on the optimization of single thread algorithm,while the parallel fault simulation research in multi-core architecture is relatively less.The existing literature is generally based on data parallelism,that is,parallel simulation of multiple faults at the same time,which requires a large amount of memory.However,this paper is mainly based on task parallelism to avoid the problem of excessive memory overhead.Based on the PPSFP algorithm in fault simulation,this paper takes the traditional architecture of the processor mapped to the architecture of multi-core CPU to realized the logic circuit fault simulation acceleration.The main contributions and achievements are summarized as follows:(1)Based on task parallelism,the fault simulation algorithm of logic circuit is improved to realize the parallel simulation of single fault(2)The existing data structure is improved to fit the multi-core architecture better.Open CL is chosen as the multi-core programming platform.Open CL is a heterogeneous architecture platform supporting a variety of hardware devices,which has good portability.In this paper,the benchmark circuit recognized by academia is taken as the experimental object to realize the purpose of accelerating fault simulation based on multicore CPU architecture.