Design And Implementation Of Pseudo-random Coded Harmonic Radar Based On Carrier Ranging And Pulse Compression Technology

Harmonic radar is a device for detecting,identifying and judging targets.It is often used in the military to detect stealth aircraft,stealth ships and other targets.It can detect nonlinear target by receiving and processing harmonic signals that scattered by nonlinear targets.The harmonic radar is extremely sensitive to semiconductors and metals.Thus,it is good at detecting equipment such as hidden communication terminals,pinhole cameras and micro-detonators.Therefore,the civilian use of harmonic radar is becoming more and more important.This paper discovered one key issue that the existing civil harmonic radars cannot complete range measurement in near-field detection.Therefore,it is necessary to design a system of micro digital and low-cost handheld harmonic radar.This paper has finished the waveform design,architecture design and has implemented each subsystem of harmonic radar in FPGA.In order to solve the problem of insufficient hardware resources,based on the systolic array architecture,this paper independently designed a complete multiplexed hardware acceleration network through C/C++ and Verilog mixed programming,and customized the Valid-Ready handshake protocol to resolve potential conflicts in network scheduling.By scheduling the data of different modules on the network in time division for calculation,the real-time signal processing capability of the system is improved,and the hardware resource consumption is greatly reduced.The waveform generation module based on the CORDIC algorithm,the interaction logic and the control logic are designed in the transmitter subsystem,thereby transmitter subsystem achieve the functions of generating the transmitted waveform and driving the peripheral chip.The carrier tracking and synchronization subsystem reconstructs the traditional carrier tracking loop,tracks the echo with a modulated signal and outputs the carrier through the mirrored NCO to provide a stable carrier signal for the target detection subsystem and the carrier ranging subsystem.The target detection subsystem adopts the two-phase coded pulse compression radar receiver scheme,and uses distributed algorithms and hardware acceleration networks to realize the implementation in FPGA.The carrier ranging subsystem uses the CORDIC algorithm to construct a high-precision two-quadrant phase detector,and realizes the function of high-precision ranging in FPGA.The paper simplifies the echo model of the non-linear node in the steady state based on the related research findings on the field of non-linear node small-signal modeling.It can simulate echo signals of harmonic radars in different noise environments,which can fill the gap on failing to cover the different situations with the measured data.This paper verifies each subsystem by the measured data and the simulation data.The test results show that each subsystem designed suggested by the paper can effectively reach its expected functions.