| As a special processor in the field of digital signal processing,DSP is widely used in various signal processing machines.Because its application scenarios are mostly scenarios that require high efficiency and high real-time performance,the current popular multi-core,very long instruction word,and single instruction multiple data,superscalar and other technologies make the architecture of DSP become more and more complex,and it is difficult for ordinary users to write software that can give full play to the performance of the processor.Therefore,how to give full play to the performance advantages of DSP and how to improve the development efficiency of real-time signal processing systems has become a focus issue.The goal of this paper is to realize and optimize the filtering algorithm in the common algorithms of digital signal processing based on the high-performance HXDSP1042 processor platform,so that the running rate of the filtering algorithm on the platform is improved.The key to optimizing the filtering algorithm on the HXDSP1042 platform is to improve the code’s use efficiency of the processor,memory and other hardware.In view of the above-mentioned problems,this paper conducts in-depth research based on the domestic HXDSP1042,and implements parallel optimization of the filtering algorithm in the basic signal processing function library built by it.Based on the hardware resources carried by HXDSP1042,the filtering algorithm is optimized mainly from two aspects:(1)Algorithm-level optimization.This paper adopts a general filtering method that conforms to the principle of library functions and is easy to optimize.Without changing the filtering results,the useless workload in the filtering process is greatly reduced,and the reused data is transmitted by macro transmission to reduce the cost of data access and improve the execution efficiency of the filtering algorithm.(2)Code-level optimization is mainly realized through parallel optimization design methods,namely special instruction adaptation,loop unrolling,and strengthening instruction parallelism.Among them,special instruction rewriting can achieve the purpose of reducing the amount of code and improving the efficiency of program execution;loop unrolling is mainly to optimize the loop operation,which can increase the number of data involved in the operation of each cycle,thereby effectively reducing the total execution of the loop number of times:By strengthening instruction parallelism,the order of instruction execution can be adjusted and optimized,thereby reducing pipeline loop and waiting time,and at the same time allowing various computing components to fully operate.The experimental results show that the theoretical running time and test error of the optimized filter algorithm have reached the corresponding library function design technical indicators,that is,the actual running time is less than 1.5 times the theoretical running time,and the error of the test results are both within 1e^(-7)Nearby distribution.By comparing the serial filtering algorithm before assembly optimization with the parallel algorithm after assembly optimization,the result shows that the average speedup ratio of the optimized filtering algorithm function reaches 24.62.Finally,by comparing with the algorithm of the same function on the high-performance processor TMS320C6678,the average efficiency improvement ratio of the filtering algorithm studied in this paper has reached 5.47,which has obvious advantages in performance,that is,the optimization of FIR filtering algorithm based on the HXDSP1042 architecture proposed in this paper can significantly improve the calculation performance of the filtering algorithm.The work results of this article have reference significance for the optimization of other software on the same platform. |
