Research On Collaborative Optimization For Multi-core Processor Resources

With the increasing intensity of numerous cores integrated into the chip,the issue today is focused on the resource management for multi-core processor systems.On the one hand,multi-core processors are widely used in various domains such as general-purpose computing,embedded system,high-performance computing and so on.As multiple types of application being in use,a growing computation requirement caused a major design bottleneck driven by energy efficiency.On the other hand,the demand of processor system for on-chip communication quality is also rising simultaneously.In order to accommodate more on-chip resources,the on-chip network with great reusability and expandability of resource can further improve the throughput of multi-core processor system,thus becomes the new multi-core interconnect standard.The network-on-chip has been applied to certain commercial processors,and well developed in some mainstream architecture simulators(such as gem5).Under a certain router micro-architecture,the design of routing algorithm in the on-chip network greatly affects the on-chip communication capabilities.Energy-efficient multi-core processor systems that use on-chip network interconnection have broad application prospects.Based on the classic heterogeneous multi-core processor architecture ARM big.LITTLE,the work designs different dynamic voltage and frequency scaling schemes to study the optimization space of energy efficiency.In order to make full use of the idle period of the processor during task execution,the voltage and frequency are dynamically adjusted to achieve the trade-off between delay and energy consumption in the system without affecting the minimum timing requirements for task execution.In order to improve energy efficiency in a fine-grained manner,offline analysis is performed on the processor system during the execution of parallel programs to determine the optimal voltage and frequency pair configuration for each task,which can further improve energy efficiency compared with the traditional online voltage and frequency adjustment scheme.This work uses gem5 simulator to realize performance and power consumption simulation,and tests with popular benchmark suites in the full system mode.Under the same simulator environment,the design of multiple routing algorithms is put forward in a single network on a chip to implement a reinforcement learning routing algorithm based on adaptive exploration.In the environment of network-onchip,the appropriate routing algorithm is selected according to different injection rates to optimize the network throughput and communication delay.Through controllers applying with three different reinforcement learning algorithm,the work integrates the Garnet model into the gem5 simulator for validation.Experimental results show that under a heterogeneous processor architecture with high energy efficiency itself,the use of dynamic voltage and frequency scaling can achieve rather energy efficiency improvements,where the offline solution has the best result.The proposed multiple routing algorithm has several times improvement in throughput and greatly reduced average delay,compared with the traditional single routing algorithm.