Research On Processor-level Error Detection And Recovery Technology Of Embedded SoC

With the advent of the Industry 4.0 era,embedded microcontrollers are playing an increasingly significant role in the development of industrial automation.The demand for chip performance in modern application scenarios is gradually increasing.Compared with single-core processor chips,embedded multi-core So C can bring great performance improvements.Meanwhile,chips continue to develop features such as miniaturization,light weight and low power consumption,which increase the sensitivity of individual devices and the probability of error,bringing severe challenges to chip reliability.How can the embedded multi-core So C give full play to the advantages of hardware resources in different computing or control applications is a question worth exploring.Multi-scenario applications of embedded So C are often oriented to perform computing or precision control tasks and have different processor load requirements,therefore the requirements for performance and reliability are not the same.For reliability requirements,traditional processor fault tolerance methods have poor real-time performance,or excessive resource consumption and high performance overhead.For the problem of resource utilization of multi-core chips,the commonly used hardware fault-tolerant processors design often consume a large amount of redundant resources to only meet the reliability requirements and apply to a single application scenario.Based on the existing researches,this paper explores the fault tolerance of multi-core processors and multi-scenario applications.Regard of reliability issues,this paper proposes a processor fault-tolerant architecture that supports three-mode redundancy at the maximum by investigating and analyzing processor fault tolerance methods.The fault shielding is completed through the majority voting mechanism,and it supports out-of-synchronization monitoring and resynchronization functions,which can exert its fault tolerance advantages in high-reliability applications.For multi-scenario applications,in order to improve the flexibility and configurability of processor redundancy,this paper explores the implementation of multi-mode configurable processors.The fault-tolerant system can be configured into three modes: In performance mode,the three processors have independent external input and output signals,and the system is equivalent to a three-core system;In the normal mode,two processors form a dual-mode lock-step fault-tolerant processor,and the other processor works independently.The So C system is equivalent to a dual-core system;In reliable mode,three processors form three-mode redundancy,which has the strongest fault tolerance.In addition to the static configuration mode,it also implements a dynamic switching function.In order to effectively verify the fault tolerance of the system,this paper proposes a random fault generator based on the investigation of the soft fault model.Using the random fault injection method,the system's fault tolerance and computing performance were tested and verified on the simulation and FPGA platform.Experimental results show that the fault generator proposed in this paper can effectively generate soft error.The simulation and FPGA implementation results show that the multi-core system has good performance in area consumption,fault tolerance performance and computing performance.Among them,redundant register resources occupy less than 25%.The single-bit fault tolerance of conventional mode and reliable mode is strong,and the 10x10 matrix multiplication calculation results show that the system performance loss is only 1.61% in the normal mode.In response to multi-scenario application problems,this paper tests the static configuration and dynamic switching functions of each mode.The experiment proves that the system can switch and return modes when the processor executes tasks,which verifies the feasibility of the system's fault tolerance and performance optimization scheme.