Research On Sparse Sampling And Prediction Method For Addressable WAT Based On Gaussian Process Regression

Integrated Circuit(IC)manufacturing is a highly complex processing process that directly affects the yield of final IC products and has a very important impact on product profits.As the feature sizes of IC continues to shrink,process fluctuations in the manufacturing process are on the increase.The fluctuations often result in a decline in yield.The electrical characteristic parameters of IC products can reflect the stability of the manufacturing process.Thus,how to capture the variations in the electrical characteristic parameters of IC products more efficiently and how to control the IC manufacturing process more accurately is a key step to ensure the yield of IC products.Wafer Acceptance Test(WAT)is an important test link in IC manufacturing.It is also a way to capture the electrical characteristic parameters of IC.WAT is mainly to test the electrical characteristics of the devices on the wafer and capture the variations of the electrical parameters.After capture the variations,it can be better to control the IC manufacturing process.As a general,if all structures on the wafer are tested,it leads to too many tests and high test costs.Therefore,in practice,the method of predicting after sparse sampling is introduced.Using the sampling-prediction method to reduce the number of test points can achieve low test cost on-wafer parameter variation capture.However,there are also certain test errors.Focused on the special structure of the addressable test chip(ATC),this thesis proposes a parameter test result prediction method suitable for addressable WAT using sparse sampling and Gaussian Process Regression(GPR).The main research is as follows:(1)Analyzing the special structure of the ATC;Investigating the current mainstream sparse sampling prediction methods;Explaining the limitation of the current mainstream methods in the application of the addressable WAT: There is a higher density of the test structures in each test chip,and the parameter variations inside each test chip must be considered when capturing the electrical characteristic parameter variations.The current mainstream methods only analyze the parameter variations at the level of the entire wafer.(2)Proposing a prediction model suitable for addressable WAT—Dual Component Prediction Model(DCPM).The variations are divided into two parts: intradie variations and inter-die variations.Using the GPR and sparse sampling,the two variation models can be built.Finally,the two models are integrated to obtain the modelling of the parameter variations on the wafer.Using the real-world addressable WAT dataset,the average error of prediction of the DCPM method is only 25% of that of other methods in the cases of the same sample number.The results of the experiment reflect the effectiveness of the DCPM which improves the accuracy of model prediction to a large extent.(3)Presenting a sparse sampling method that combines randomness and coverage to train the model efficiently—Partition Random Sampling(PRS).The sampling method first divides some same area as possible on the wafer and then randomly samples in each area.PRS can ensure the sparse sampling points evenly distributed on the wafer without losing randomness,which ensures the representativeness of the sampling data.Through simulation experiments,the prediction method using PRS can obtain more accurate prediction results on the same data set.Through experiments on the real-world addressable WAT dataset,this thesis proves that prediction in the application of PRS and DCPM has better performance than one of the current mainstream methods—the Gaussian Process Model(GPM).