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Design Of Key Control Circuits Of Buck Converter

Posted on:2008-06-05Degree:MasterType:Thesis
Country:ChinaCandidate:M M SunFull Text:PDF
GTID:2178360215958781Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
As the heart of the electronic system, the power supply develops fast with the fast development of the electric devices, and the requirement is more and more high. The switch mode power supply (SMSP) is called as the high efficiency power supply. It has many virtues such as wide stable output ranges, large power density ratio, lightness and good performance. Its fewer losses on the switch bring it high efficiency compared with the linear regulator. The highest efficiency of the switch mode power supply could be above 90% and it is widely used in the portable applications. Therefore, it is of great importance to research into the switch mode power supply. The paper is supported by Nation Science Foundation of China and Sichuan Province Academic Foundation.The basic principle and control techniques of DC-DC buck converters are described in detail. The advantages and disadvantages of the control methods are analyzed and compared, and where each method is more adapted to is pointed out.The key control circuits based on DC-DC buck converter in current control mode which is used in mobile applications and portable applications are designed: the PWM sum-comparator and the current control comparator of synchronous reifications. The operational principle, structure and small signal character are particularly analyzed. To solve the problems in PWM Current mode method, a slope circuit based on the principle of slope compensation is designed.The PWM control circuit is the core of converters which realized the control algorithm. Its performance is very important in converters. The low power losses synchronous reification (SR) is widely applied in low power DC converters. The SR control method can effectively solve the problem that the efficiency is too low in light loads.A new type of PWM comparators is designed: the sum-comparator. It replaces the error amplifier and improves the performance: the gain is approximately 120DB. And the current control comparator of synchronous reifications can adjust the threshold to the load. Its gain is approximately 96DB. The circuits are designed in BiCMOS 0.6um process. Simulate the circuits with HSPICE and the results indicate that the design have achieved the expected characteristics. The system simulations verify the function of the designed circuits.
Keywords/Search Tags:buck converter, PWM, synchronous reifications, slope compensation
PDF Full Text Request
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