Design And Verification Of ADC Structure For Cascading To Improve Resolution

The rapid development of wireless communication,aerospace and intelligent detection requires high resolution and high conversion speed of analog-to-digital converter(ADC).In the maturity structure of ADC,successive approximation ADC(SAR),incremental accumulation(?-?)ADC is a representative of the high resolution ADC,its resolution can reach 24,but only in the level of KSPS conversion rate;Full parallel(Flash)ADC can achieve GSPS conversion speed,but its resolution is difficult to achieve more than 8 bits.The PIPELINE ADC structure is an improvement of the low resolution of the full parallel ADC,but under the condition of high conversion speed,its resolution is still difficult to achieve more than 16 bits.The traditional two-step formula interval structure divides the analog-to-digital conversion process into coarse conversion process and fine conversion process,which is also an improvement of the parallel structure.However,its development is limited by the lack of obvious resolution improvement and the huge resistor voltage division network.In view of the mature architecture ADC has its own emphasis on resolution and conversion speed,this paper makes some innovation on the structure of the analog-to-digital converter,and proposes two kinds of high-performance cascaded ADC designs with both high resolution and high conversion rate.In this paper,on the basis of the traditional structure of pipeline ADC,an improved structure of the MDAC module type allowance transfer cascade structure is proposed.This structure does not use inter stage amplifier with simple structure of the switch gate array instead of complex structure of DAC module,reduce complexity and noise is introduced into the system,the cascade structure ADC system in dynamic characteristics and power consumption and area are improved.The two-stage 16-bit system is modeled and simulated by the ideal device model based on Verilog-A,and the feasibility of the structure is verified.This article also puts forward a reference voltage relay type seed interval ADC cascade structure,this kind of structure on the basis of the traditional two step formulas interval ADC to its partial pressure resistance network scale is improved,but also increase the throughput between the magnitude and the design of inter stage synchronous circuit,makes the structure also has the traditional two step formulas interval structure that the extensibility.A two-stage 16-bit sub stage 8-bit system is modeled and simulated by the ideal device model based on Verilog-A,and the feasibility of the structure is verified.Based on the feasibility of sub interval reference voltage transfer cascading structure,a two-stage 16-bit system with a conversion rate of 50 MSPS was designed by CMOS technology based on 0.18 um process,and the functional simulation and dynamic characteristic simulation were carried out.The simulation results show that the SNR is about 107.58 dB,the SNR is about 89.05 dB,the SFDR is about 98.38 dBC,the THD is about 0.0035%,and the effective resolution is about 14.49 bit.