Design Of High-Power And High-Efficiency RDSS Terminal Power Amplifier Chip

With the official networking of the Third-Generation Bei Dou system,China has realized a true global navigation system.The positioning and short message service of the Bei Dou system have higher requirements on the transmission distance,power consumption,and signal quality of satellite communication and navigation terminal equipment.Therefore,the power amplifier,as the main device that determines the terminal signal processing capability,requires higher output power,higher efficiency,and better linearity.To solve the problem that the efficiency,power,and linearity of the power amplifier are difficult to balance each other,this paper specifically studies a high-power application in the satellite radio positioning system(Radio Determination Satel-lite System,RDSS)High-efficiency power amplifier chips have good reference value for engineering applications.This article first designed a 5W RDSS power amplifier die based on the InGaP/GaAsHBT MMIC process,and then designed a 10W RDSS power amplifier chip using off-chip power synthesis technology and LGA packaging technology.The main research work of this paper are as follows:1.Complete the 5W RDSS power amplifier die circuit and layout design:determine the amplifier structure,complete the HBT die design at all levels,design the on-chip matching circuit and stability circuit,and design an adaptive linearization temperature-insensitive bias based on the mirror current source structure,which solves the problem of bias point drift caused by temperature rise and input power increase,and improves linearity;2.Complete the circuit and layout design of the 10W RDSS power amplifier chip:study the orthogonal power synthesis technology.design the power distribution and synthesis network based on the±45°phase shift,so that the amplifiers of the upper and lower branches work in the orthogonal state and improve the load mismatch tolerance.Based on harmonic suppression technology,design an off-chip output matching circuit to suppress high-order harmonics of the power amplifier and improve efficiency;3.Based on the ADS,HFSS and ANSYS platforms,design a 10W RDSS power amplifier chip based on the LGA package,and conduct an iterative optimization simulation of its circuit,electromagnetic and thermal characteristics.The chip works at1.6?1.65GHz,when the collector-emitter bias voltage is 5V,the linear gain is 38.177 dB,the gain flatness is±0.11 dB,the input standing wave ratio in the frequency band is less than 1.17:1,and the output standing wave ratio is less than 1.52:1,P1dB=40.336dBm,P_SAT=41.06dBm,PAE@P_1dB?32.69%,PAE@P_SAT?35.17%,IMD3?-37dBc@(P2tone_1dB-3dB),chip size is 6mm×6mm×1mm.The 10W RDSS power amplifier chip designed in this paper can also ensure thermal stability under high output power conditions and has a certain tolerance for load mismatch.The results of the pre-simulation and post-simulation show that the chip meets the design specifications and has good power,efficiency and linearity characteristics.