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EMI Noise Analysis And Suppression Techniques For Superjunction MOSFET

Posted on:2022-10-14Degree:MasterType:Thesis
Country:ChinaCandidate:Q GuoFull Text:PDF
GTID:2518306524487164Subject:IC Engineering
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Because of its high input impedance,good temperature stability,low noise and other advantages,MOSFET has become the core responsible for signal processing and energy conversion in the field of high voltage and large current.At the same time,MOSFET has no minority storage effect,fast switching speed,and is the mainstream power device responsible for DC-DC conversion.However,when the power MOSFET device works as the power switch of the switching power supply,the drain voltage and current change rapidly in a short time.The large dv/dt and di/dt lead to the electric field coupling and magnetic field coupling,and the whole circuit system appears Electromagnetic Interference(EMI)problem.The superjunction MOSFET breaks the silicon limit and has smaller on-resistance under the same voltage resistance,compared with the traditional MOSFET,the size can be designed to be smaller,so there is less parasitic capacitance and switching loss.There are EMI noise problems that are more serious than traditional MOSFET.In this paper,the switching process and EMI radiated noise generation mechanism for superjunction MOSFET are investigated,achievable suppression schemes are proposed,favourable results have been obtained in wafer verification.The main content are as follows:Firstly,through simulation analysis of depletion layer variation and carrier concentration distribution under different voltages,the special peak phenomenon of Miller capacitance Cgd?Vds curve of superjunction MOSFET device is explained,and the design parameters that affect the size and slope of Cgd?Vds curve are proposed.Then,the design parameters are simulated from the point of view of superjunction MOSFET device design,twelve effective EMI suppression measures are summarized.These measures are thinning thickness of oxide layer,increasing the cell number of parallel,augmenting the length of Gate,minishing the PN column width simultaneously,decreasing N column width relativly,decreasing PN column concentration at the same time,increasing N column concentration relativly,non-uniform P column with shallow upper and deep lower doping,increasing the interval of discontinuous P column,decreasing the length of PN column,minishing the thickness of buffer layer relativly,and augmenting the N+doping concentration for JFET region.The EMI generation mechanism of three kinds of superjunction MOSFET devices is also verified.Further,a Cgd?Vds curve equivalent switching model for superjunction MOSFET is proposed,which points out that the maximum of Cds/Cgd*|k|affects the overshoot voltage(?Vm)in switching process for superjunction MOSFET,shows that the larger Cgd and the flat Cgd?Vds curve can suppress the EMI noise of the superjunction device in the switching circuit.Finally,through the chip design of gate electrode,voltage column width and voltage column doping balance,six kinds of 600V superjunction MOSFET devices are measured for capacitance waveform,switch waveform and EMI noise,thus verifying the above Cgd?Vds curve and the correlation simulation of switch waveform,which fully proves the feasibility of the switch model.By means of the suppression technology,the horizontal EMI noise of the superjunction MOSFET device can be reduced by 10.9%at most and the vertical EMI noise can be reduced by 11.2%at most under the condition that the other electrical parameters are all up to the standard.The results provide a design basis for EMI noise optimization of superjunction MOSFET devices.
Keywords/Search Tags:Cgd, dv/dt, EMI, SJ-MOSFET
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