Design And Implementation Of Frequency Offset Estimation And Digital Predistortion Algorithms Of Repeater In WCDMA

This dissertation discusses the design and implementation of frequency offset estimation and digital predistortion algorithms of WCDMA repeater.Firstly, the paper reviews the most likelihood estimation algorithm (ML) which is based on the CPICH in WCDMA. The method has very good performance which could be seen from the simulation figure. In the figure, we could see that even when the SNR is -20dB and the real frequency offset is 1660Hz, the error of estimated frequency offset is only approximately 2.2Hz. In addition, this method uses FFT to simplify the processing, so the process of estimation is comparatively simply.Secondly, this dissertation fully summarizes the modeling of the memoryless power amplifiers, predistortion of memoryless power amplifier, the modeling of power amplifiers with memory effects, and predistortion of power amplifiers with memory effects. Then we particularly analyze memory polynomial predistorter design. Through the 4 examples with different power amplifier models, it could be proved that the polynomial predistorter is suitable for quite a large number of power amplifiers and it has strong robustness, and it also could be proved that this method could nearly fully suppress the spectral regrowth.Finally, the dissertation analyzes the hardware implementation of ML estimation and memory polynomial predistorter algorithms. The two algorithms are implemented on BF561 from ADI Corporation. The dissertation shows their Hardware design scheme, and gives the fixed-point qualification scheme. At last, it gives the performance figure. These figures depict that in ML algorithm even when the SNR is -18dB and the real frequency offset is 1660, the error of estimated frequency offset is 1.6Hz and it takes only 1.1ms to fulfill the whole ML algorithm. In the memory polynomial predistorter algorithm the hardware performance is very similar to the floating-point and the time to complete the memory polynomial predistorter algorithm is only 1.9987s, because of the use of two cores and DMA technique in Bf561.