Design Of FPGA Neural Network Accelerator For Sound Event Detection

Sound as an important medium for people to perceive the things around,is found in all aspects of people's lives,and it often contains important information to assist people in making decisions.Sound Event Detection(SED)refers to classifying the collected audio data and judging the current event or the scene in which it is located.It has broad applications in the fields of unmanned driving,smart home,security monitoring,etc.With the continuous development of deep learning technology in various fields,the use of neural networks to replace traditional audio recognition methods has become the choice of more and more researchers.As one of the classic algorithms in deep learning,convolutional neural networks have achieved great success in image classification,target detection and other fields.In the field of sound event detection,convolutional neural networks have also surpassed other neural network algorithms and has become the most popular algorithm in this field.At present,the main implementation of convolutional neural networks is still on GPUs.However,sound event detection systems often need to be deployed on embedded terminals.The huge power consumption of GPUs has become a major obstacle to system deployment.At this time,the researchers focused their attention on the FPGA.The low power consumption,low latency,and programmable characteristics of the FPGA are very suitable for the forward reasoning work of the convolutional neural network,and it's parallelism also provides powerful computing power for convolution neural network.Based on FPGA,this paper proposes a parallel hardware structure between convolution kernels for sound event detection.This paper first uses a specific structure of convolutional neural network based on the sound event data set Urbansound8 k.The convolutional neural network algorithm designed in this paper has a 9-layer structure,and the recognition accuracy of the algorithm can reach 85%.The input feature map of the network uses the logarithmic mel spectrogram of sound events,and then a specific hardware network architecture is designed for the network.After analyzing the parallelism characteristics of convolutional neural networks,it is determined that the parallelism between convolutional cores will be used as the parallelism scheme of the system.At the same time,in order to make the network easy to implement on the hardware and without affecting the accuracy of network recognition,simplify the operation of the softmax layer in the hardware architecture,the hardware circuit in this article is written in Verilog HDL language.Finally,the paper carried out functional verification and calculation speed test on the hardware acceleration system.Use the Vivado to test the core module convolution calculation module and the overall module of the system,and verify the accuracy of the data reading and calculation of the convolution calculation module and the correctness of the overall system module.The system speed test results show that when the FPGA clock frequency is 100 MHz,its operation speed has obvious advantages compared with the CPU platform,which meets the design requirements.hardware design of this article gives full play to the advantages of FPGA parallelism and computing power,and has certain reference significance for actual engineering practice.